[21] | 1 | %\def\TBresp{\coussy} |
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| 2 | %\def\TBresplab{\labsticc} |
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| 3 | %\def\TBpartner{\alllabs,\allcompagnies} |
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| 4 | |
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| 5 | \begin{taskinfo} |
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| 6 | \let\UPMC\leader |
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| 7 | \let\ALL\enable |
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| 8 | \end{taskinfo} |
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| 9 | % |
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| 10 | \begin{objectif} |
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| 11 | This task relies to the main features for embedded system. |
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| 12 | Its objective consists of the specification of designer input, of the |
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| 13 | definition of the hardware architectural templates and of all the features |
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| 14 | that the HAS tools share. |
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| 15 | \end{objectif} |
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| 16 | % |
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| 17 | \begin{workpackage}{T1} |
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| 18 | \item This \ST specifies COACH for the system designer. At this |
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| 19 | level COACH is a black box. The deliverable is a document allowing the system |
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| 20 | designers to use COACH: feeding it (inputs), how to use it (design flow), |
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| 21 | what COACH can generate (definition of the generic architecture of the |
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| 22 | MPSoC and its 3 targets hardware mapping). |
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| 23 | \begin{livrable} |
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| 24 | \item{-1-V1}{0}{6}{d}{LIP6}{user manual} |
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| 25 | The first milestone of the document for allowing demonstration |
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| 26 | \ST to start. |
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| 27 | \item{-1-V1}{6}{18}{d}{LIP6}{user manual} |
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| 28 | The second milestone takes into account the missing features |
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| 29 | the demonstrators rise. |
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| 30 | \item{-1-VF}{18}{30}{d}{LIP6}{user manual} |
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| 31 | Final release. |
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| 32 | \end{livrable} |
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| 33 | \item This \ST specifies the software COACH structure. The deliverable is a |
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| 34 | document listing all the COACH software components and how they cooperate. |
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| 35 | \begin{livrable} |
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| 36 | \item{}{0}{6}{d}{LIP6}{decription of software architecture} |
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| 37 | It contains the software list and the data flow among them. |
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| 38 | \end{livrable} |
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| 39 | \item This \ST specifies the \xcoach format. |
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| 40 | \begin{livrable} |
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| 41 | \item{-1-V1}{0}{6}{d x}{LIP}{specification of \xcoach format} |
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| 42 | First release of the XML specification of the \xcoach format |
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| 43 | and its associated documentation allowing to start HLS tools development. |
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| 44 | \item{-1-V2}{6}{12}{d x}{LIP}{specification of \xcoach format} |
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| 45 | Second release of XML specification of the \xcoach format |
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| 46 | taking into account the corrections and modifications that the |
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| 47 | developers of HLS tools rise. |
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| 48 | \item{-1-VF}{12}{18}{d x}{LIP}{C++ to \xcoach format} |
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| 49 | Release of XML specification of the \xcoach format enhanced with |
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| 50 | the expression of loop potential. |
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| 51 | \item{-2-V1}{0}{12}{x x}{\ubs}{C++ to/from \xcoach format} |
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| 52 | The first executable generates a \xcoach description |
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| 53 | version \taskname-3-V1 from a C++ description of a task defined in \ST |
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| 54 | \taskname-1. |
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| 55 | The second program regenerates a C description from a \xcoach |
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| 56 | description. |
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| 57 | \item{-2-VF}{12}{18}{x x}{\ubs}{C++ to/from \xcoach format} |
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| 58 | The same programs as the former but for \xcoach format version \name-3-V2. |
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| 59 | \item{-3-V1}{0}{18}{x}{LIP6}{\xcoach format to SystemC} |
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| 60 | The first release of a program that translates \xcoach description to CABA |
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| 61 | and TLM-DT SystemC. |
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| 62 | \item{-3-VF}{18}{24}{x}{LIP6}{\xcoach format to SystemC} |
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| 63 | The \name-3-V1 deliverable without bugs reported by the demonstrators. |
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| 64 | \item{-4-V1}{0}{18}{x}{\ubs}{\xcoach format to VHDL} |
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| 65 | The first release of a program that translates \xcoach description to |
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| 66 | synthesizable VHDL description. |
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| 67 | \item{-4-VF}{18}{24}{x}{\ubs}{\xcoach format to VHDL} |
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| 68 | The \name-4-V1 deliverable without bugs reported by the demonstrators. |
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| 69 | \end{livrable} |
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| 70 | \item Backend HLS tools use a characterized macro-cell library to build the |
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| 71 | micro-architecture of a coprocessor. The characterisation of a cell dépends |
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| 72 | on the target device. The role of this \ST is to define the macro-cells and |
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| 73 | to provite a tool that characterizes them automatically by synthesizing them |
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| 74 | and by extracting their delays. This is done by using RTL synthesis. |
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| 75 | \begin{livrable} |
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| 76 | \item{-1-VF}{0}{6}{d}{\ubs}{macro-cell definition} |
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| 77 | The document define the macro cell and the file format describing them. |
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| 78 | \item{-2-VF}{0}{12}{x}{\ubs}{macro-cell library generator} |
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| 79 | A progam that generates automatically the characterized macro-cell library |
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| 80 | for a FPGA device. |
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| 81 | \end{livrable} |
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| 82 | \end{workpackage} |
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