source: anr/task-1.tex @ 120

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1\begin{taskinfo}
2\let\UPMC\leader
3\let\ALL\enable
4\end{taskinfo}
5%
6\begin{objectif}
7This task deals with the main features of digital systems.
8Its objectives are the specification of the designer input, the
9definition of the hardware architectural templates and of all the features
10that the HAS tools will share.
11\end{objectif}
12%
13\begin{workpackage}
14\item This \ST specifies the COACH environment for the system designer. At this
15    level the COACH framework is a black box. The deliverables are documents
16    specifying: how to feed COACH (the inputs), how to use COACH (the design flow),
17    what is generated (the outputs).
18    %(definition of the generic architecture of the
19    %MPSoC and its 3 targets hardware mapping).
20    \begin{livrable}
21    \itemV{0}{6}{d}{\Supmc}{COACH specification} \setMacroInAuxFile{specGenManualI}
22        The first version of the COACH specification.
23        This document contains the general description of the framework, the design flow and the
24        description of the architectural templates.
25        It refers to the HAS specification (delivrable {\specHasManual}) and
26        to the CSG specifcation (delivrable \specCsgManual) for the COACH input
27        descriptions.
28    \itemL{6}{12}{d}{\Supmc}{COACH specification}{1:0:0} \setMacroInAuxFile{specGenManual}
29        The final version of the {\specGenManualI} delivrable updated with the \mustbecompleted{FIXME:: first ?}
30            feed-backs of the demonstrator \STs.
31    \itemV{0}{6}{d}{\Stima}{CSG specification} \setMacroInAuxFile{specCsgManualI}
32        The first version of the CSG (COACH System Generator) specification.
33        It specifies how the task graph is described, the communication schemes and its
34        associated API (Application  Programming Interface).
35        The base is the SRL library and the MWMR communication component defined by the SocLib
36        ANR project.
37        Nevertheless, these basic schemes will be enhanced to allow more efficient
38        synthesis.
39    \itemL{6}{12}{d}{\Stima}{CSG specification}{1:0:0} \setMacroInAuxFile{specCsgManual}
40        The final version of the {\specGenManualI} delivrable updated with the \mustbecompleted{FIXME:: first ?}
41            feed-backs of the demonstrator \STs.
42    \itemV{0}{6}{d}{\Subs}{HAS specification} \setMacroInAuxFile{specHasManualI}
43        The first version of the HAS (Hardware Accelerator Synthesis) specification.
44        It specifies how tasks must be written (C/C++ subset) and how
45        communication schemes defined in the {\specCsgManual} delivrable must be described for
46        coprocessor synthesis.
47    \itemL{6}{12}{d}{\Subs}{HAS specification}{1:0:0} \setMacroInAuxFile{specHasManual}
48        The final version of the {\specGenManualI} delivrable updated with the \mustbecompleted{FIXME:: first ?}
49            feed-backs of the demonstrator \STs.
50    \end{livrable}
51\item This \ST specifies the software COACH structure. The deliverable is a
52    document listing all the COACH software components and how they cooperate.
53    \begin{livrable}
54    \itemL{0}{6}{d}{\Supmc}{decription of \ganttlf software architecture}{1:0:0}
55        It contains the software list and the data flow among them.
56    \end{livrable}
57\item This \ST specifies the \xcoach format.
58    \begin{livrable}
59    \itemV{0}{6}{d+x}{\Slip}{\xcoach format specification}
60        \setMacroInAuxFile{specXcoachDocI}
61        First release of the XML specification of the \xcoach format (DTD)
62        and its associated documentation allowing to start HLS tools development.
63    \itemV{6}{12}{d+x}{\Slip}{\xcoach format specification}
64        \setMacroInAuxFile{specXcoachDocII}
65        Second release of XML specification of the \xcoach format
66        taking into account the corrections and modifications that the
67        developers of HAS tools suggested.
68    \itemL{12}{18}{d+x}{\Slip}{\xcoach format specification}{0:0:0}
69        \setMacroInAuxFile{specXcoachDoc}
70        Last release of XML specification of the \xcoach format enhanced with
71        the expression of loop potential parallelism.
72    \itemV{6}{12}{x}{\Subs}{C/C++ $\leftrightarrow$ \xcoach format (1)}
73        \setMacroInAuxFile{specXcoachToCAI}
74        A GCC plugin C2X that generates a \xcoach description
75        (defined in {\specXcoachDocI} deliverable) from a C/C++ task description
76        (defined in {\specHasManual} deliverable).
77    \itemL{12}{18}{x}{\Subs}{C++ $\leftrightarrow$ \xcoach format (1)}{0:0:0}
78        \setMacroInAuxFile{specXcoachToCA}
79        The same software as the former (\specXcoachToCAI) but for \xcoach format defined
80        in the {\specXcoachDoc} deliverable and HAS input defined in the {\specHasManual}
81        deliverable.
82    \itemV{7}{12}{x}{\Subs}{C/C++ $\leftrightarrow$ \xcoach format (2)}
83        \setMacroInAuxFile{specXcoachToCBI}
84        This second tool X2C regenerates a C description from a \xcoach
85        description.
86    \itemL{12}{18}{x}{\Subs}{C++ $\leftrightarrow$ \xcoach format (2)}{0:0:0}
87        \setMacroInAuxFile{specXcoachToCB}
88        The same software as the former (\specXcoachToCBI) but for the \xcoach format as defined
89        in the {\specXcoachDoc} deliverable and HAS input as defined in the {\specHasManual}
90        deliverable.
91    \itemV{12}{18}{x}{\Supmc}{\xcoachplus format to SystemC}
92        \setMacroInAuxFile{specXcoachToSystemCI}
93        The first release of the software tool X2SC  that translates \xcoachplus description to CABA
94        and TLM-DT SystemC module.
95    \itemL{18}{24}{x}{\Supmc}{\xcoachplus format to SystemC}{0:2:0}
96        \setMacroInAuxFile{specXcoachToSystemC}
97        Maintenance work of the former software (\specXcoachToSystemCI).
98    \itemV{12}{18}{x}{\Subs}{\xcoachplus format to VHDL}
99        \setMacroInAuxFile{specXcoachToVhdlI}
100        The first release of the softwaretool X2VHDL that translates \xcoachplus description to
101        synthesizable VHDL description.
102    \itemL{18}{24}{x}{\Subs}{\xcoachplus format to VHDL}{0:0:0}
103        \setMacroInAuxFile{specXcoachToVhdl}
104        Maintenance work of the former software (\specXcoachToVhdlI) and integration
105        of enhancements proposed in \novers{\specXilinxOptimization} deliverable.
106    \itemL{18}{21}{d}{\Sxilinx}{\xilinx RTL optimisation (1)}{0:3:0}
107        \setMacroInAuxFile{specXilinxOptimization}
108        This deliverable consists in optimizing the VHDL generated from \xcoachplus format
109        (deliverable \novers{\specXcoachToVhdl}) to the \xilinx RTL synthesis tools.
110        \ubs will provide several examples of VHDL source files generated from \xcoachplus,
111        with explanations about generation process of main data structures used in VHDL sources,
112        \xilinx will provide back a documentation listing that proposes VHDL generation enhancements.
113    \end{livrable}
114   
115\item This \ST aims to define a tool in order to pilot the GCC/xcoach compiler.
116\mustbecompleted{FIXME: UBS :: Cette section et ses livrables doivent etre retouches}
117    \begin{livrable}
118    \itemL{0}{3}{d}{\Subs}{GCC/xcoach driver definition}{0:0:0}
119        This document specifies the way the GCC driver tool drives GCC.
120    \itemL{3}{9}{x}{\Subs}{GCC/xcoach driver generator}{0:0:0}
121        Release of the GCC driver tool.
122    \end{livrable}
123
124\item Backend HLS tools use a characterized macro-cell library to build the
125    micro-architecture of a coprocessor. The characterisation of a cell depends
126    on the target device. The role of this \ST is to define the macro-cells and
127    to provite a tool that characterizes them automatically by synthesizing them
128    and by extracting their delays. This is done by using RTL synthesis.
129    \begin{livrable}
130    \itemL{0}{6}{d}{\Subs}{macro-cell definition}{0:0:0}
131        The document defines the macro cell and the file format describing them.
132    \itemL{6}{12}{x}{\Subs}{macro-cell library generator}{0:0:0}
133        A software tool that generates automatically the characterized macro-cell library
134        for a FPGA device.
135    \end{livrable}
136\end{workpackage}
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