\begin{taskinfo} \let\UPMC\leader \let\ALL\enable \end{taskinfo} % \begin{objectif} This task relies to the main features for embedded system. Its objective consists of the specification of designer input, of the definition of the hardware architectural templates and of all the features that the HAS tools share. \end{objectif} % \begin{workpackage}{D1} \item This \ST specifies COACH for the system designer. At this level COACH is a black box. The deliverable is a document allowing the system designers to use COACH: feeding it (inputs), how to use it (design flow), what COACH can generate (definition of the generic architecture of the MPSoC and its 3 targets hardware mapping). \begin{livrable} \item{-1-V1}{0}{6}{d}{LIP6}{user manual} The first milestone of the document for allowing demonstration \ST to start. \item{-1-V1}{6}{18}{d}{LIP6}{user manual} The second milestone takes into account the missing features the demonstrators rise. \item{-1-VF}{18}{30}{d}{LIP6}{user manual} Final release. \end{livrable} \item This \ST specifies the software COACH structure. The deliverable is a document listing all the COACH software components and how they cooperate. \begin{livrable} \item{}{0}{6}{d}{LIP6}{decription of software architecture} It contains the software list and the data flow among them. \end{livrable} \item This \ST specifies the \xcoach format. \begin{livrable} \item{-1-V1}{0}{6}{d x}{LIP}{specification of \xcoach format} First release of the XML specification of the \xcoach format and its associated documentation allowing to start HLS tools development. \item{-1-V2}{6}{12}{d x}{LIP}{specification of \xcoach format} Second release of XML specification of the \xcoach format taking into account the corrections and modifications that the developers of HLS tools rise. \item{-1-VF}{12}{18}{d x}{LIP}{C++ to \xcoach format} Release of XML specification of the \xcoach format enhanced with the expression of loop potential. \item{-2-V1}{0}{12}{x x}{\ubs}{C++ to/from \xcoach format} The first executable generates a \xcoach description version \taskname-3-V1 from a C++ description of a task defined in \ST \taskname-1. The second program regenerates a C description from a \xcoach description. \item{-2-VF}{12}{18}{x x}{\ubs}{C++ to/from \xcoach format} \global\edef\STcTOxcoach{\name} The same programs as the former but for \xcoach format version \name-3-V2. \item{-3-V1}{0}{18}{x}{LIP6}{\xcoach format to SystemC} The first release of a program that translates \xcoach description to CABA and TLM-DT SystemC. \item{-3-VF}{18}{24}{x}{LIP6}{\xcoach format to SystemC} \global\edef\STxcoachTOsystemc{\name} The \name-3-V1 deliverable without bugs reported by the demonstrators. \item{-4-V1}{0}{18}{x}{\ubs}{\xcoach format to VHDL} The first release of a program that translates \xcoach description to synthesizable VHDL description. \item{-4-VF}{18}{24}{x}{\ubs}{\xcoach format to VHDL} \global\edef\STxcoachTOvhdl{\name} The \name-4-V1 deliverable without bugs reported by the demonstrators. \end{livrable} \item Backend HLS tools use a characterized macro-cell library to build the micro-architecture of a coprocessor. The characterisation of a cell dépends on the target device. The role of this \ST is to define the macro-cells and to provite a tool that characterizes them automatically by synthesizing them and by extracting their delays. This is done by using RTL synthesis. \begin{livrable} \item{-1-VF}{0}{6}{d}{\ubs}{macro-cell definition} The document define the macro cell and the file format describing them. \item{-2-VF}{0}{12}{x}{\ubs}{macro-cell library generator} A progam that generates automatically the characterized macro-cell library for a FPGA device. \end{livrable} \end{workpackage}