source: anr/task-2.tex @ 74

\begin{taskinfo}
\let\UPMC\leader
\let\IRISA\enable
\let\TIMA\enable
\end{taskinfo}
%
\begin{objectif}
This task deals with the prototyping and the generation of FPGA-SoC digital systems.
Its is described on figure~\ref{archi-csg}.
Its objective is to allow the system designer to explore the system space design by
quickly prototyping and then to generate automatically the FPGA-SoC system.
This task consists of
\begin{itemize}
\item the development of all the missing components (SytemC model and/or synthesizable VHDL description),
\item the configuration and the development of drivers of the operating systems,
\item the CSG software that generates the simulators for prototyping and the FPGA-SoC system,
\item the specification of enhanced communication schemes and their sofware and hardware implementation.
\end{itemize}
This task being based on the SocLib platform, a first release will be delivrable at $T0+12$
to allow the demonstrators to start working.
This release will include the standard communication schemes (base on SocLib MWMR component)
and support the COACH architectural template for prototyping and hardware generation.
\end{objectif}
%
\begin{workpackage}
\item This \ST corresponds to the Coach System Generator (CSG) software.
    \begin{livrable}
    \itemV{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch}
        \mustbecompleted{FIXME: LIP6 :: Pas clair pour un non expert du projet... ET remplacement de "milestone" par
    "CSG release"} 
        The first milestone that will allow demonstrators to start working using the COACH
        hardware architecture template.
    \itemV{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly}
        This milestone adds to CSG the support to the XILINX and ALTERA architectural
        templates and to the enhanced communication system.
        In this milestone only the SystemC prototyping will be supported for the XILINX
        and ALTERA architectural template.
        HAS is available.
    \itemV{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch}
        This milestone extends CSG (\csgPrototypingOnly) to
        FPGA-SoC generation for the XILINX and ALTERA architectural template.
    \itemL{24}{36}{x}{\Supmc}{CSG}{6:6:6}
        Maintenance work of CSG.
    \end{livrable}
\item This \ST deals with the components of the architectural template.
    \\
    For the COACH architectural template, it consists of the devlopment of the VHDL
    synthesizable description of the missing components. Notice that the SystemC models
    comes from the SocLib ANR project, the processor with its cache comes from the TSAR
    ANR project.
    \\
    For the XILINX and ALTERA architectural template, we use the XILINX and ALTERA IPs.
    The missing component is the MWMR used for communication between the tasks of the
    application.
    \begin{livrable}
    \itemL{0}{12}{h}{\Supmc}{COACH architecture}{1:0:0}
        The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components.
    \itemV{6}{18}{x}{\Stima}{XILINX architecture}
        \setMacroInAuxFile{csgXilinxSystemC}
        The SystemC simulation module of the MWMR component with a PLB bus interface plus
        the SystemC modules of the components of the XILINX architectural template
        not available in the SocLib component library.
    \itemL{18}{24}{h}{\Stima}{XILINX architecture}{9:9:0}
        The synthesizable VHDL description of the MWMR component corresponding to the
        SystemC module of the former delivrable (\csgXilinxSystemC).
    \itemV{6}{18}{x}{\Sirisa}{ALTERA architecture}
        \setMacroInAuxFile{csgAlteraSystemC}
        The SystemC simulation module of the MWMR component with an AVALON bus interface plus
        the SystemC modules of the components of the ALTERA architectural template
        not available in the SocLib component library.
    \itemL{18}{24}{h}{\Sirisa}{ALTERA architecture}{0:0:0}
        The synthesizable VHDL description of the MWMR component corresponding to the
        SystemC module of the former delivrable (\csgAlteraSystemC);
    \itemV{6}{12}{d}{\Subs}{UBS communication adapter}
       \setMacroInAuxFile{gautCOMMoptimization}
       Specification of an optimized communication adapter (space and time) component to handle data interleaving.
       This evolution aims to solve out of order communication weakness of the classical MWMR. 
    \itemV{12}{24}{x}{\Subs}{UBS communication adapter}
       First release of the tool that generates the VHDL description of the optimized communication adapter
       and its corresponding SystemC module. 
    \itemL{24}{30}{x}{\Subs}{UBS communication adapter}{0:0:0}
       Final release of the tool that generates the VHDL description of the optimized communication adapter
       and its corresponding SystemC module (\gautCOMMoptimization).
    \end{livrable}
\item This \ST consists of the configuration of the SocLib MUTEK and DNA operating
    system and the development of drivers for the hardware architectural templates
    and enhanced communication schemes defined in \novers{\specCsgManual} delivrable.
    For the ALTERA and XILINX architectural template, the OSs must also be ported on
    the NIOS2 and MICROBLAZE processors.
    \begin{livrable}
    \itemV{6}{8}{x}{\Supmc}{MUTEK OS}
        The drivers required for the first CSG milestone (delivrable \csgCoachArch).
    \itemV{8}{18}{x}{\Supmc}{MUTEK 0S}
        The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
    \itemL{18}{33}{x}{\Supmc}{MUTEK OS}{1:1:2}
        Maintenance work.
    \itemL{6}{18}{x}{\Supmc}{Port of MUTEK OS}{1.0:1:0}
        Port of MUTEK OS on the NIOS2 and MICROBLAZE processors.
    \itemV{6}{8}{x}{\Stima}{DNA OS}
        The drivers required for the first CSG milestone (delivrable \csgCoachArch).
    \itemV{8}{18}{x}{\Stima}{DNA 0S}
        The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
    \itemL{18}{33}{x}{\Stima}{DNA OS}{6:3:2}
        Maintenance work.
    \itemL{6}{18}{x}{\Stima}{Port of DNA OS}{3:1:0}
        Port of DNA OS on the NIOS2 and MICROBLAZE processors.
    \end{livrable}
\end{workpackage}