[26] | 1 | \begin{taskinfo} |
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| 2 | \let\LIP\leader |
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| 3 | \let\IRISA\enable |
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| 4 | \end{taskinfo} |
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| 5 | % |
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| 6 | \begin{objectif} |
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[41] | 7 | The objective of this task is to convert the input specification of |
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| 8 | an hardware accelerator, which must be written in a familiar language |
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| 9 | (C/C++) with as few constraints as possible, into a form suitable for |
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| 10 | the HLS tools. If the target is an ASIP, the frontend has to extract |
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| 11 | patterns from the source code and convert them into the definition |
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| 12 | of an extensible processor. If the target is a process network, the |
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| 13 | front end has to distribute the workload and the data sets as fairly |
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| 14 | as possible, identify communication channels, and output an \xcoach |
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| 15 | description. |
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[26] | 16 | \end{objectif} |
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| 17 | % |
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[52] | 18 | \begin{workpackage} |
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| 19 | \item Extraction de motifs et regénération au format COACH annoté |
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[26] | 20 | \mustbecompleted{FIXME:IRISA ........} |
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| 21 | \begin{livrable} |
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[52] | 22 | \itemV{0}{18}{d}{\Sirisa}{Interation manuelle des motifs} |
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| 23 | \mustbecompleted{FIXME .....} |
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| 24 | \itemL{18}{24}{d}{\Sirisa}{Integration manuelle des motifs}{0:0:0} |
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| 25 | \mustbecompleted{FIXME ......} |
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[26] | 26 | \end{livrable} |
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[52] | 27 | \item \mustbecompleted{FIXME: la liste des ST est dans wp.txt} |
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[26] | 28 | \begin{livrable} |
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[52] | 29 | \itemL{0}{18}{d}{\Sirisa}{Intégration manuelle des motifs}{0:0:0} |
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| 30 | \mustbecompleted{FIXME ......} |
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[26] | 31 | \end{livrable} |
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[52] | 32 | \item Extraction of parallelism in polyhedral loops and conversion into a process network. |
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[41] | 33 | \begin{livrable} |
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[52] | 34 | \itemV{0}{6}{d}{\Slip}{Method, Preliminary Definition} |
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[42] | 35 | Description of the process network construction method. User manual. |
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[52] | 36 | \itemL{30}{36}{d}{\Slip}{Method}{0:0:0} |
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[42] | 37 | Final assessment of the method and improved version of the user manual. |
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[52] | 38 | \itemV{6}{12}{x}{\Slip}{Process Construction)} |
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[42] | 39 | Preliminary implementation in the Syntol framework. At this step the sofware will |
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| 40 | just implement a single constructor. |
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[52] | 41 | \itemV{12}{24}{x}{\Slip} {Arrays and FIFO} |
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[42] | 42 | Implementation of the array contraction and FIFO construction algorithm. Conversion |
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| 43 | of the imput and output to the \xcoach format. |
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[52] | 44 | \itemL{24}{30}{x}{\Slip} {Process ans FIFO Construction} {0:0:0} |
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[42] | 45 | Final release taking into account the feedbacks from the demonstrator \STs. |
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[41] | 46 | \end{livrable} |
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| 47 | \end{workpackage} |
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| 48 | |
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| 49 | |
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| 50 | |
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