source: anr/task-3.tex @ 88

\begin{taskinfo}
\let\LIP\leader
\let\IRISA\enable
\end{taskinfo}
%
\begin{objectif}
The objective of this task is to convert the input specification of
an hardware accelerator, which must be written in a familiar language
(C/C++) with as few constraints as possible, into a form suitable for
the HLS tools. If the target is an ASIP, the frontend has to extract 
patterns from the source code and convert them into the definition
of an extensible processor. If the target is a process network, the
front end has to distribute the workload and the data sets as fairly
as possible, identify communication channels, and output an \xcoach
description.
\end{objectif}
%
\begin{workpackage}
  \item This sub-task aims at providing compiler support for custom instructions 
  within the HAS front-end. It will take as input the COACH intermediate 
  representation, and will output an annotated COACH IR containing the custom
  instructions definitions along with their occurrence in the application.

    \begin{livrable}
      \itemV{0}{18}{d}{\Sirisa}{Instruction selection for user defined custom instructions}
        In this first version of the software, the computations patterns corresponding to
        custom instruction are specified by the user, and then automatically extracted (when
        beneficial) from the application intermediate representation. 
        %\mustbecompleted{FIXME .....}
      \itemL{18}{24}{d}{\Sirisa}{Automatic extraction of patterns}{0:0:0}
        In this second version, the software will also be able to automatically identify 
        interesting pattern candidates in the application code, and use them as custom 
        instructions.  
    \end{livrable}
 
 \item In this sub-task, we provide micro-architectural template models for the two target
 processor architectures (NIOS-II and MIPS) supported within in the COACH-ASIP design flow. 
 For each processor, we provide a simulation model (System-C) and a synthesizable model (VHDL) 
 of the architecture, along with its architectural extensions 
    \begin{livrable}
      \itemV{0}{12}{d}{\Sirisa}{SystemC Model for an simple extensible MIPS architectural template}
      \itemV{0}{18}{d}{\Sirisa}{VHDL Model for an simple extensible MIPS architectural template}
                %\mustbecompleted{FIXME .....}
      \itemL{0}{12}{d}{\Sirisa}{SystemC Model for an extensible NIOS processor template, the VHDL model being already available from Altera}{0:0:0}

      \itemV{0}{24}{d}{\Sirisa}{SystemC Model for a extensible MIPS with tight
      architectural integration of its instruction set extensions}
      \itemV{0}{24}{d}{\Sirisa}{VHDL Model for a extensible MIPS with tight
      architectural integration of its instruction set extensions}
      \itemL{0}{36}{d}{\Sirisa}{Evaluation report }{0:0:0}

    \end{livrable}

  \item Extraction of parallelism in polyhedral loops and conversion into a process network.

   \begin{livrable}
    \itemV{0}{6}{d}{\Slip}{Method, Preliminary Definition}
      Description of the process network construction method for programs with 
      polyhedral loops. User manual.
    \itemL{30}{36}{d}{\Slip}{Process generation method}{0:0:0}
      Final assessment of the method and improved version of the user manual.
    \itemV{6}{12}{x}{\Slip}{Process construction)}
      Preliminary implementation in the Syntol framework. 
      At this step the software will just implement a single constructor.
    \itemV{12}{18}{x}{\Slip} {Arrays and FIFO}
      Implementation of the array contraction and FIFO construction algorithm. 
      Conversion of the input and output to the \xcoach format.
    \itemV{18}{30}{d+x}{\Slip}{Non-polyhedral extension}
      Extension of automatic parallelization and array contraction
      to non-polyhedral loops. Implementation in the Bee framework.
    \itemL{30}{36}{x}{\Slip} {Process and FIFO construction} {0:0:0}
      Final release taking into account the feedbacks from the 
      demonstrator \STs.
   \end{livrable}

\end{workpackage}