\begin{taskinfo}
\let\LIP\leader
\let\IRISA\enable
\end{taskinfo}
%
\begin{objectif}
The objective of this task is to convert the input specification of
an hardware accelerator, which must be written in a familiar language
(C/C++) with as few constraints as possible, into a form suitable for
the HLS tools. If the target is an ASIP, the frontend has to extract 
patterns from the source code and convert them into the definition
of an extensible processor. If the target is a process network, the
front end has to distribute the workload and the data sets as fairly
as possible, identify communication channels, and output an \xcoach
description.
\end{objectif}
%
\begin{workpackage}
  \item Extraction de motifs et regénération au format COACH annoté
    \mustbecompleted{FIXME:IRISA ........}
    \begin{livrable}
      \itemV{0}{18}{d}{\Sirisa}{Interation manuelle des motifs}
        \mustbecompleted{FIXME .....}
      \itemL{18}{24}{d}{\Sirisa}{Integration manuelle des motifs}{0:0:0}
        \mustbecompleted{FIXME ......}
    \end{livrable}
  \item \mustbecompleted{FIXME: la liste des ST est dans wp.txt}
    \begin{livrable}
        \itemL{0}{18}{d}{\Sirisa}{Intégration manuelle des motifs}{0:0:0}
        \mustbecompleted{FIXME ......}
    \end{livrable}
  \item Extraction of parallelism in polyhedral loops and conversion
    into a process network.
   \begin{livrable}
    \itemV{0}{6}{d}{\Slip}{Method, Preliminary Definition}
      Description of the process network construction method. User manual.
    \itemL{30}{36}{d}{\Slip}{Method}{0:0:0}
      Final assessment of the method and improved version of the user manual.
    \itemV{6}{12}{x}{\Slip}{Process Construction)}
      Preliminary implementation in the Syntol framework. 
      At this step the sofware will just implement a single constructor.
    \itemV{12}{18}{x}{\Slip} {Arrays and FIFO}
      Implementation of the array contraction and FIFO construction algorithm. 
      Conversion of the input and output to the \xcoach format.
    \itemV{18}{30}{x}{\Slip} {Beyond the polytope model}
      Extension of automatic parallelization and array contraction
      to non-polyhedral loops.
    \itemL{30}{36}{x}{\Slip} {Process ans FIFO Construction} {0:0:0}
      Final release taking into account the feedbacks from the 
      demonstrator \STs.
   \end{livrable}

\end{workpackage}