1 | \begin{taskinfo} |
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2 | \let\UBS\leader |
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3 | \let\UPMC\enable |
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4 | \let\TIMA\enable |
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5 | \end{taskinfo} |
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6 | % |
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7 | \begin{objectif} |
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8 | This objectives of this task are to provides the 2 HAS back-ends of the COACH project and |
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9 | a tool that adapt the coprocessor frequency to the FPGA-SoC frequency. This later is given |
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10 | by the processors and the BUS. |
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11 | \\ |
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12 | The HAS back-ends as shown figure~\ref{archi-hls} reads \xcoach data and provides |
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13 | \xcoachplus data that is \xcoach format annotated with hardware information such as |
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14 | variable binded on register, operation binded on cell and sheduled. The \xcoach format |
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15 | being generated by {\specXcoachToC} deliverable and \xcoachplus being treated by |
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16 | \novers{\specXcoachToSystemC} and \novers{\specXcoachToVhdl} deliverables, |
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17 | this task is very dependent of the task~1. |
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18 | \par |
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19 | For the two HAS front-end, this task is based on the already existing HLS tools GAUT and |
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20 | tools. These tools are complementary and not competitor because they cover irespectively |
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21 | data and control dominated orthogonal domain. |
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22 | The organization of the task is firstly to integrate quickly the existing HLS to the COACH |
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23 | framework. Secondly these tools will be improved to allows to treat data dominated application |
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24 | with a few control for GAUT and control dominated application with a few data treatment |
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25 | for UGH. This will enlarge the domain the HLS can cover. |
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26 | \end{objectif} |
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27 | % |
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28 | \begin{workpackage}{D4} |
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29 | \item The goal of this \ST is to integrate the UGH HLS tool to the COACH framework. It |
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30 | consists of suppressing the C commpiler and the SystemC and VHDL drivers and replacing |
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31 | them by \xcoach and \xcoachplus drivers. |
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32 | \begin{livrable} |
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33 | \item{V1}{6}{12}{x}{\Stima}{UGH integration} The UGH software that is able to read |
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34 | \xcoach format. |
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35 | \item{V2}{12}{18}{x}{\Supmc}{UGH integration} The UGH software that is able to read |
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36 | \xcoach format and to write \xcoachplus format. |
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37 | \item{VF}{18}{33}{x}{\Supmc}{UGH integration} Maintenance work of the UGH software. |
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38 | \end{livrable} |
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39 | \item The goal of this \ST is to integrate the GAUT HLS tool to the COACH framework. It |
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40 | consists of suppressing the C commpiler and the SystemC and VHDL drivers and replacing |
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41 | them by \xcoach and \xcoachplus drivers. |
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42 | \begin{livrable} |
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43 | \item{V1}{6}{12}{x}{\Stima}{GAUT integration} The GAUT software that is able to read |
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44 | \xcoach format. |
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45 | \item{VF}{12}{18}{x}{\Stima}{GAUT integration} The GAUT software that is able to read |
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46 | \xcoach format and to write \xcoachplus format. |
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47 | \end{livrable} |
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48 | \item The goal of this \ST is to improve the UGH and GAUT HLS tools. |
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49 | UGH and GAUT experimentations have shown respectively 2 and \mustbecompleted{FIXME:2} |
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50 | usefull enhancements |
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51 | \begin{livrable} |
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52 | \item{}{18}{24}{x}{\Stima}{UGH enhancement 1} The UGH software whith support for treating |
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53 | automatically data dominated sections included into a control dominated application. |
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54 | \item{}{21}{27}{x}{\Stima}{UGH enhancement 2} The UGH software that is able to |
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55 | generate an micro-architecture without the variable binding currently done by the |
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56 | designer. |
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57 | \item{}{18}{24}{x}{\Subs}{GAUT enhancement 1} A GAUT excutable that is able to |
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58 | \mustbecompleted{FIXME:UBS: ........}. |
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59 | \item{}{21}{27}{x}{\Subs}{GAUT enhancement 2} A GAUT excutable that is able to |
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60 | \mustbecompleted{FIXME:UBS: ........}. |
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61 | \item{}{21}{27}{x}{\Subs}{GAUT enhancement 2} A GAUT excutable that is able to |
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62 | \mustbecompleted{FIXME:UBS: ........}. |
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63 | \end{livrable} |
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64 | \item In FPGA-SoC, the frequency is given by the processors and the BUS. The coprocessors |
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65 | generated by HLS synthesis must respect this frequency. However, the HLS tools can not |
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66 | guarantee that the micro-architectures they generate, respect accurately this |
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67 | frequency. This is especially the case when the target is a FPGA device, because the |
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68 | delays are really known only after the RTL synthesis and that estimated delays used |
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69 | by the HLS are very imprecis. The goal of this \ST is to provide a feature to adapt |
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70 | the coprocessors frequency to the FPGA-SoC frequency after the coprocessor RTL |
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71 | synthesis. |
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72 | \begin{livrable} |
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73 | \item{V1}{0}{6}{d}{\Supmc}{frequency calibration} A document describing the set up of |
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74 | the coprocessor frequency calibration. |
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75 | \item{V2}{6}{12}{x}{\Supmc}{frequency calibration} A VHDL description of hardware |
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76 | added to the coprocessor to enable the calibration. |
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77 | \item{VF}{12}{24}{x}{\Supmc}{frequency calibration} The frequency calibration software |
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78 | consists of a driver in the FPGA-SoC operating system and of a control software on |
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79 | a PC. |
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80 | \end{livrable} |
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81 | \end{workpackage} |
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