source: anr/task-4.tex @ 67

\begin{taskinfo}
\let\UBS\leader
\let\UPMC\enable
\let\TIMA\enable
\end{taskinfo}
%
\begin{objectif}
The objectives of this task are to provide the two HAS back-ends of the COACH project and
a tool that adapt the coprocessor frequency to the FPGA-SoC frequency as given 
by the processors and the BUS.
%pourquoi en majuscule?
\\
The HAS back-ends as shown in figure~\ref{archi-hls} reads \xcoach data and provides
\xcoachplus data, i.e. \xcoach data annotated with hardware information such as
variables bindings to registers, operations bindings to cells and a schedule. The \xcoach format
being generated by \novers{\specXcoachToCA} deliverable and \xcoachplus being treated by
\novers{\specXcoachToSystemC} and \novers{\specXcoachToVhdl} deliverables,
this task is very dependent on task~1.
\par
For the two HAS front-end, this task is based on the already existing HLS tools GAUT and
UGH. These tools are complementary and not in competition because they cover respectively
data and control dominated designs.
The organization of the task is firstly to integrate quickly the existing HLS to the COACH
framework. Secondly these tools will be improved to allows to treat data dominated application
with a few control for GAUT and control dominated application with a few data processing
for UGH. This will enlarge the domain the HLS can cover.
\end{objectif}
%
\begin{workpackage}
\item The goal of this \ST is to integrate the UGH HLS tool to the COACH framework. It
    consists of suppressing the C compiler and the SystemC and VHDL drivers and replacing
    them by \xcoach and \xcoachplus drivers.
    \begin{livrable}
    \itemL{6}{12}{x}{\Stima}{UGH integration}{12:0:0}
        The UGH software that is able to read \xcoach format.
    \itemV{12}{18}{x}{\Supmc}{UGH integration}
        The UGH software that is able to read \xcoach format and to write \xcoachplus format.
    \itemL{18}{33}{x}{\Supmc}{UGH integration}{0:2:4.0}
        Maintenance work of the UGH software.
    \end{livrable}
\item The goal of this \ST is to integrate the GAUT HLS tool to the COACH framework. It
    consists of suppressing the C commpiler and the SystemC and VHDL drivers and replacing
    them by \xcoach and \xcoachplus drivers.
    \begin{livrable}
    \itemV{6}{12}{x}{\Subs}{GAUT integration}
        The GAUT software that is able to read \xcoach format.
    \itemV{12}{18}{x}{\Subs}{GAUT integration}
        The GAUT software that is able to read \xcoach format and to write \xcoachplus format.
    \itemL{18}{33}{x}{\Subs}{GAUT integration}{0:0:0}
        Maintenance work of the GAUT software.
    \end{livrable}
\item The goal of this \ST is to improve the UGH and GAUT HLS tools.
    UGH and GAUT experimentations have shown respectively 2 and \mustbecompleted{FIXME:2}
    usefull enhancements
    \begin{livrable}
    \itemL{18}{24}{x}{\Stima}{UGH enhancement 1}{0:9:0}
        The UGH software whith support for treating automatically data dominated sections
        included into a control dominated application.
    \itemL{21}{27}{x}{\Stima}{UGH enhancement 2}{0:3:6}
        The UGH software that is able to generate a micro-architecture without the
        variable binding currently done by the designer.
    \itemL{6}{18}{x}{\Subs}{GAUT enhancement 1}{0:0:0}
        Release of the GAUT software that supports the control and data flow formal model.
\mustbecompleted{FIXME:USB ca ne va pas avec l'intro de la tache, UGH n'a
plus aucune utilite si ceci reste}
    \itemL{18}{30}{x}{\Subs}{GAUT enhancement 2}{0:0:0}
        Release of the GAUT software that supports the control and data flow formal model
        and also supports new constraints and objectives defined in
        \mustbecompleted{FIXME:USB utilise une macro svp: \ST1-1}
        \mustbecompleted{FIXME:UBS: quel delivrable ??}.
%   FIXME:USB redondant avec le delivrable "GAUT integration" ou alors
%   c'est en enhancement et il faut le decrire.
%    \item{VF}{30}{36}{x}{\Subs}{GAUT enhancement 3} Final release of the GAUT software
    \end{livrable}
\item In FPGA-SoC, the frequency is given by the processors and the BUS. The coprocessors
    generated by HLS synthesis must respect this frequency. However, the HLS tools can not
    guarantee that the micro-architectures they generate accurately respect this
    frequency. This is especially the case when the target is a FPGA device, because the
    delays are really known only after the RTL synthesis and that estimated delays used
    by the HLS are very imprecize. The goal of this \ST is to provide a tool to adapt
    the coprocessors frequency to the FPGA-SoC frequency after the coprocessor RTL
    synthesis.
    \begin{livrable}
    \itemV{0}{12}{d}{\Supmc}{frequency calibration}
        A document describing the set up of the coprocessor frequency calibration.
    \itemV{12}{24}{x}{\Supmc}{frequency calibration}
        A VHDL description of hardware added to the coprocessor to enable the calibration.
    \itemL{24}{33}{x}{\Supmc}{frequency calibration}{2:.5:3.5}
        The frequency calibration software consists of a driver in the FPGA-SoC operating
        system and of a control software on a PC.
    \end{livrable}
\end{workpackage}