\begin{taskinfo} \let\UBS\leader \let\UPMC\enable \let\TIMA\enable \let\XILINX\enable \end{taskinfo} % \begin{objectif} The objectives of this task are to provide the two HAS back-ends of the COACH project and a tool that adapt the coprocessor frequency to the FPGA-SoC frequency as required by the processors and the system bus. \\ The HAS back-ends as shown in figure~\ref{archi-hls} reads an \xcoach description and provides an \xcoachplus description, i.e. an \xcoach description annotated with hardware information such as variables binding to registers, operations bindings to cells/fonctional units, operation scheduling... The \xcoach format being generated by the \novers{\specXcoachToCA} deliverable and the \xcoachplus being treated by the \novers{\specXcoachToSystemC} and the \novers{\specXcoachToVhdl} deliverables, this task strongly depends on task~1. \par For the two HAS front-end, this task is based on the already existing HLS tools GAUT and UGH. These tools are complementary and not in competition because they cover respectively data and control dominated designs. \end{objectif} \begin{workpackage} \subtask{Making HAS back-end to read \xcoach format} The goal of this \ST is to integrate the UGH and GAUT HLS tool to the COACH framework. by implementing the mechanism to read \xcoach format. \begin{livrable} \itemL{6}{12}{x}{\Stima}{UGH integration}{12:0:0} Release of the UGH software that reads \xcoach format. \itemL{6}{12}{x}{\Subs}{GAUT release reading \xcoach}{6:0:0} Release of the GAUT software that is able to read \xcoach format. \end{livrable} % \subtask{Making HAS back-end to write \xcoachplus format} The goal of this \ST is to integrate the UGH and GAUT HLS tool to the COACH framework. by implementing the mechanism to write \xcoachplus format. \begin{livrable} \itemL{12}{18}{x}{\Supmc}{UGH integration}{0:2:4.0} Release of the UGH software that writes \xcoachplus format. \itemL{12}{18}{x}{\Subs}{GAUT release writing \xcoachplus}{0:6:0} Release of the GAUT software that is able to read \xcoach format and to write \xcoachplus format. \end{livrable} \subtask{Coprocessor frequency adaptation} In FPGA-SoC, the frequency is given by the processor(s) and the system BUS. The coprocessors generated by HLS synthesis must respect this frequency. However, the HLS tools can not guarantee that the micro-architectures they generate accurately respect this frequency. This is especially the case when the target is a FPGA device, because the delays are really known only after the RTL synthesis and that estimated delays used by the HLS are very inaccurate. The goal of this \ST is to provide a tool that adapts the coprocessors frequency to the FPGA-SoC frequency after the coprocessor RTL synthesis. \begin{livrable} \itemV{0}{12}{d}{\Supmc}{Frequency calibration} A document describing the set up of the coprocessor frequency calibration. \itemV{12}{24}{x}{\Supmc}{Frequency calibration} \setMacroInAuxFile{freqCalibrationVhdl} A VHDL description of hardware added to the coprocessor to enable the calibration. \itemL{24}{33}{x}{\Supmc}{Frequency calibration}{2:.5:3.5} The frequency calibration software consists of a driver in the FPGA-SoC operating system and of a control software. \end{livrable} \end{workpackage}