source: anr/task-4.tex @ 26

Last change on this file since 26 was 26, checked in by coach, 14 years ago
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1\begin{taskinfo}
2\let\UBS\leader
3\let\UPMC\enable
4\let\TIMA\enable
5\end{taskinfo}
6%
7\begin{objectif}
8This objectives of this task are to provides the 2 HAS back-ends of the COACH project and
9a tool that adapt the coprocessor frequency to the FPGA-SoC frequency. This later is given
10by the processors and the BUS.
11\\
12The HAS back-ends as shown figure~\ref{archi-hls} reads \xcoach data and provides
13\xcoachplus data that is \xcoach format annotated with hardware information such as
14variable binded on register, operation binded on cell and sheduled. The \xcoach format
15being generated by {\STcTOxcoach} \ST and \xcoachplus being treated by {\STxcoachTOsystemc}
16and {\STxcoachTOvhdl} \STs, this task is very dependent of task-1 task.
17\par
18For the two HAS front-end, this task is based on the already existing HLS tools GAUT and
19tools. These tools are complementary and not competitor because they cover irespectively
20data and control dominated orthogonal domain.
21The organization of the task is firstly to integrate quickly the existing HLS to the COACH
22framework. Secondly these tools will be improved to allows to treat data dominated application
23with a few control for GAUT and control dominated application with a few data treatment
24for UGH. This will enlarge the domain the HLS can cover.
25\end{objectif}
26%
27\begin{workpackage}{D4}
28\item The goal of this \ST is to integrate the UGH HLS tool to the COACH framework. It
29    consists of suppressing the C commpiler and the SystemC and VHDL drivers and replacing
30    them by \xcoach and \xcoachplus drivers.
31    \begin{livrable}
32    \item{-V1}{6}{12}{x}{\tima}{UGH integration} An executable that is able to read
33        \xcoach format.
34    \item{-VF}{12}{18}{x}{\tima}{UGH integration} An executable that is able to read
35        \xcoach format and to write \xcoachplus format.
36    \end{livrable}
37\item The goal of this \ST is to integrate the GAUT HLS tool to the COACH framework. It
38    consists of suppressing the C commpiler and the SystemC and VHDL drivers and replacing
39    them by \xcoach and \xcoachplus drivers.
40    \begin{livrable}
41    \item{-V1}{6}{12}{x}{\tima}{GAUT integration} An executable that is able to read
42        \xcoach format.
43    \item{-VF}{12}{18}{x}{\tima}{GAUT integration} An executable that is able to read
44        \xcoach format and to write \xcoachplus format.
45    \end{livrable}
46\item The goal of this \ST is to improve the UGH and GAUT HLS tools.
47    UGH and GAUT experimentations have shown respectively 2 and \mustbecompleted{FIXME:2}
48    usefull enhancements
49    \begin{livrable}
50    \item{-1-VF}{18}{24}{x}{\tima}{UGH enhancement 1} A UGH excutable that is able to treat
51        automatically data dominated sections included into a control dominated application.
52    \item{-2-VF}{21}{27}{x}{\tima}{UGH enhancement 2} A UGH executable that is able to
53        generate an micro-architecture without the varaiable binding currently done by the
54        designer.
55    \item{-3-VF}{18}{24}{x}{\upmc}{GAUT enhancement 1} A GAUT excutable that is able to
56        \mustbecompleted{FIXME:UBS: ........}.
57    \item{-4-VF}{21}{27}{x}{\upmc}{GAUT enhancement 2} A GAUT excutable that is able to
58        \mustbecompleted{FIXME:UBS: ........}.
59    \item{-5-VF}{21}{27}{x}{\upmc}{GAUT enhancement 2} A GAUT excutable that is able to
60        \mustbecompleted{FIXME:UBS: ........}.
61    \end{livrable}
62\item In FPGA-SoC, the frequency is given by the processors and the BUS. The coprocessors
63    generated by HLS synthesis must respect this frequency. However, the HLS tools can not
64    guarantee that the micro-architectures they generate, respect accurately this
65    frequency. This is especially the case when the target is a FPGA device, because the
66    delays are really known only after the RTL synthesis and that estimated delays used
67    by the HLS are very imprecis. The goal of this \ST is to provide a feature to adapt
68    the coprocessors frequency to the FPGA-SoC frequency after the coprocessor RTL
69    synthesis.
70    \begin{livrable}
71    \item{-V1}{0}{6}{d}{\umpc}{frequency calibration} A document describing the set up of
72        the coprocessor frequency calibration.
73    \item{-V2}{6}{12}{x}{\umpc}{frequency calibration} A VHDL description of hardware
74        added to the coprocessor to enable the calibration.
75    \item{-V3}{12}{20}{x}{\umpc}{frequency calibration} The frequency calibration software
76        consists of a driver in the FPGA-SoC operating system and of a control software on
77        a PC.
78    \end{livrable}
79\end{workpackage}
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