source: anr/task-5.tex @ 23

Last change on this file since 23 was 23, checked in by coach, 15 years ago
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1\begin{taskinfo}
2\let\UPMC\leader
3\let\TIMA\enable
4\let\ALTERA\enable
5\end{taskinfo}
6%
7\begin{objectif}
8This task pools the features dedicated to HPC system design. It is described on
9figures~\ref{coach-flow} and \ref{archi-hpc}. It consists in
10\begin{itemize}
11\item Helping the HPC designer to find a good partition of the initial application
12    (figure~\ref{archi-hpc}.
13\item Providing communication schems between the software part runing on the PC and the
14FPGA-SoC.
15\item Implementing the communication schem at all levels: partition help, software
16implementation both on the PC and in the operating system of the FPGA-SoC, hardware.
17\item FPGA reconfiguration. \mustbecompleted{FIXME:TIMA}
18\end{itemize}
19The low level hardware transmission support will be the PCI/X bus which allows high bit-rate
20transfers. The reasons of this choices are that both ALTERA and Xilinx provide PCI/X IP for
21their FPGA and that GPU HPC softwares use also it.
22This will allow us at least to be inspired by GPU communication schems and may be to reuse
23parts of the GPU softwares.
24\end{objectif}
25%
26\begin{workpackage}{T5}
27\item This \ST is the definition of the communication schems as a software API
28    (Application Programing Interface) between the application part running on the PC and
29    the application part running on the FPGA-SoC.
30    \begin{livrable}
31    \item{-VF}{0}{6}{d}{\upmc}{HPC communication API} User refernce manual describing the API.
32    \end{livrable}
33\item This \ST aims with the application partitioning help. It is a library implementing
34    the communication API with features to profile the application partionning.
35    \begin{livrable}
36    \item{-VF}{0}{12}{x}{\upmc}{HPC partionning help} A library.
37    \end{livrable}
38\item This \ST aims with the implementation of the communication API on the both sides (PC
39    part and FPGA-SoC).
40    \begin{livrable}
41    \item{-1-VF}{0}{21}{x}{\upmc}{HPC API for Linux PC} 
42    \item{-2-VF}{0}{21}{x}{\tima}{HPC API for DNA OS} 
43    \item{-3-VF}{0}{21}{x}{\upmc}{HPC API for Mutek OS} 
44    \end{livrable}
45\item This \ST aims with the implementation of hardware required by the COACH
46    architectural template for using the PCI/X IP of \altera and \xilinx.
47    \begin{livrable}
48    \item{-1-VF}{0}{21}{h}{\tima}{HPC hardwre \xilinx} A synthesizable VHDL description
49        of a PLB/VCI bridge.
50    \item{-1-VF}{0}{21}{h}{\altera}{HPC hardwre \altera} A synthesizable VHDL description
51        of a AVALON/VCI bridge.
52    \end{livrable}
53\item This \ST aims with the dynamic reconfiguration of FPGA.
54    \begin{livrable}
55    \item{-1-VF}{0}{30}{x}{\tima}{dynamic reconfiguration DNA drivers}
56    \item{-2-VF}{0}{30}{x}{\upmc}{dynamic reconfiguration mutek drivers}
57    \item{-3-VF}{0}{30}{x}{\upmc}{CSG support for dynamic reconfiguration}
58    \item{-3-VF}{0}{30}{x}{\tima}{PC support for dynamic reconfiguration}
59    \end{livrable}
60\end{workpackage}
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