\begin{taskinfo}
\let\UPMC\leader
\let\TIMA\enable
\let\ALTERA\enable
\end{taskinfo}
%
\begin{objectif}
This task pools the features dedicated to HPC system design. It is described on
figures~\ref{coach-flow} and \ref{archi-hpc}. It consists in
\begin{itemize}
\item Helping the HPC designer to find a good partition of the initial application
    (figure~\ref{archi-hpc}.
\item Providing communication schems between the software part runing on the PC and the
FPGA-SoC.
\item Implementing the communication schem at all levels: partition help, software
implementation both on the PC and in the operating system of the FPGA-SoC, hardware.
\item FPGA reconfiguration. \mustbecompleted{FIXME:TIMA}
\end{itemize}
The low level hardware transmission support will be the PCI/X bus which allows high bit-rate
transfers. The reasons of this choices are that both ALTERA and Xilinx provide PCI/X IP for
their FPGA and that GPU HPC softwares use also it.
This will allow us at least to be inspired by GPU communication schems and may be to reuse
parts of the GPU softwares.
\end{objectif}
%
\begin{workpackage}{D5}
\item This \ST is the definition of the communication schems as a software API
    (Application Programing Interface) between the application part running on the PC and
    the application part running on the FPGA-SoC.
    \begin{livrable}
    \item{-VF}{0}{6}{d}{\Supmc}{HPC communication API} User refernce manual describing the API.
    \end{livrable}
\item This \ST aims with the application partitioning help. It is a library implementing
    the communication API with features to profile the application partionning.
    \begin{livrable}
    \item{-VF}{0}{12}{x}{\Supmc}{HPC partionning help} A library.
    \end{livrable}
\item This \ST aims with the implementation of the communication API on the both sides (PC
    part and FPGA-SoC).
    \begin{livrable}
    \item{-1-VF}{0}{21}{x}{\Supmc}{HPC API for Linux PC} 
    \item{-2-VF}{0}{21}{x}{\Stima}{HPC API for DNA OS} 
    \item{-3-VF}{0}{21}{x}{\Supmc}{HPC API for Mutek OS} 
    \end{livrable}
\item This \ST aims with the implementation of hardware required by the COACH
    architectural template for using the PCI/X IP of \altera and \xilinx.
    \begin{livrable}
    \item{-1-VF}{0}{21}{h}{\Stima}{HPC hardwre \xilinx} A synthesizable VHDL description
        of a PLB/VCI bridge.
    \item{-1-VF}{0}{21}{h}{\Saltera}{HPC hardwre \altera} A synthesizable VHDL description
        of a AVALON/VCI bridge.
    \end{livrable}
\item This \ST aims with the dynamic reconfiguration of FPGA.
    \begin{livrable}
    \item{-1-VF}{0}{30}{x}{\Stima}{dynamic reconfiguration DNA drivers}
    \item{-2-VF}{0}{30}{x}{\Supmc}{dynamic reconfiguration mutek drivers}
    \item{-3-VF}{0}{30}{x}{\Supmc}{CSG support for dynamic reconfiguration}
    \item{-3-VF}{0}{30}{x}{\Stima}{PC support for dynamic reconfiguration}
    \end{livrable}
\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
    with its PCI/X IP. These boards are dedicated to the COACH HPC development.
    They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
    \begin{livrable}
    \item{-VF}{0}{6}{x}{\Saltera}{HPC development boards}
    \end{livrable}
\end{workpackage}