Last change
on this file since 47 was
40,
checked in by coach, 15 years ago
|
Paul task 4 to 6 and section 4.4
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File size:
1.0 KB
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Rev | Line | |
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[23] | 1 | \begin{taskinfo} |
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| 2 | \let\IRISA\leader |
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| 3 | \let\UPMC\enable |
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| 4 | \end{taskinfo} |
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| 5 | % |
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| 6 | \begin{objectif} |
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| 7 | This task groups the demonstrators of the COACH project. |
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| 8 | The demonstrators cover various domains and application types to drive |
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| 9 | the specification choices. |
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| 10 | \end{objectif} |
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| 11 | % |
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[27] | 12 | \begin{workpackage}{D6} |
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[40] | 13 | \item This \ST is the reference demonstrator. It is an HPC application and so it covers |
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[23] | 14 | in addition to HPC (task-5) both the system genration (task-2), the HAS (task-3) and (task-4). |
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| 15 | The reference demonstrator can be a Motion JPEG application, |
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[40] | 16 | or an application that draws in 3D (under open GL) a simulation of a |
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| 17 | metor cloud attracted by a sun and planets, |
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[23] | 18 | or a database management system. |
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| 19 | \begin{livrable} |
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[36] | 20 | \item{V1}{0}{6}{x}{\Supmc}{reference demonstrator specification} Choice of the demonstrator and its |
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[23] | 21 | implementation as a PC C/C++ program. |
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[36] | 22 | \item{VF}{6}{12}{x}{\Supmc}{reference demonstrator} The demonstrator |
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[40] | 23 | split in two parts, a description as a communicating task graph of the FPGA-SoC part. |
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[23] | 24 | \end{livrable} |
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| 25 | \end{workpackage} |
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| 26 | |
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| 27 | |
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| 28 | |
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| 29 | |
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