source: anr/task-backbone.tex @ 297

\begin{taskinfo}
\let\UPMC\leader
\let\ALL\enable
\end{taskinfo}
%
\begin{objectif}
The objectives of this task are the specification of the designer input, the
definition of the hardware architectural templates and of all the features
that the HAS tools will share.
An other objective is the specification of the framework used to facilitate the 
exploitation and the integration of the core engine into an industrial flow.
\end{objectif}
%
\begin{workpackage}
\subtask{Specification of the COACH environment}
    This \ST specifies the global COACH environment for the system designer:
    the core engine which is seen as a black box associated
    with a configuration framework based on Eclipse.
    This framework will be integrated into Magillem tool suite.
    The deliverables specify 
    how to feed COACH (the inputs),
    how to use COACH (use model),
    what is generated (the outputs)
    and  how the Magillem framework interacts with the core engine.
    \begin{livrable}
    \itemV{0}{6}{d}{\Supmc}{Use model specification}
        This document describes the use model of COACH. It will be a cooperative work.
        Its main parts are:
        \begin{description}
          \item[General overview] (\Supmc)
          \item[CSG specification] (\Stima):
            here the COACH System Generator is specified:
            how the task graph is described, the communication schemes and
            its associated API (Application  Programming Interface).
            The base is the SRL library and the MWMR communication component defined
            by the SocLib ANR project.
            Nevertheless, these basic schemes will be enhanced to allow more efficient
            synthesis.
          \item[HAS specification] (\Subs):
            this part focuses to the Hardware Accelerator Synthesis.
            It specifies how tasks must be written (C/C++ subset) and how
            communication schemes must be described for coprocessor synthesis.
          \item[Magillem framework specification] (\Smds):
            this part specifies the functionalities enabling the interactions between
            Magillem and the core engine.
        \end{description}
    \itemL{6}{12}{d}{\Supmc}{Use model specification}{3:0:0}
        \setMacroInAuxFile{useModelSpecification}
        The final version of the Use model specification enhanced
        with the feed-backs of the demonstrator \STs.
        \OtherPartner{0}{12}{\Slip}   {2:0:0}
        \OtherPartner{0}{12}{\Sirisa} {2:0:0}
        \OtherPartner{0}{12}{\Stima}  {3:0:0}
        \OtherPartner{0}{12}{\Subs}   {3:0:0}
        \OtherPartner{0}{12}{\Sbull}  {2:0:0}
        \OtherPartner{0}{12}{\Sthales}{2:0:0}
        \OtherPartner{0}{12}{\Smds}   {2:0:0}
    \end{livrable}
%
\subtask{Internal software structure}
    \begin{livrable}
    \itemL{0}{6}{d}{\Supmc}{COACH internal \ganttlf software architecture}{1:0:0}
        This document lists all the COACH software components and how they cooperate.
    \end{livrable}
%
\subtask{\xcoach format}
    This \ST specifies the \xcoach and the \xcoachplus formats.
    \begin{livrable}
    \itemV{0}{6}{d+x}{\Slip}{\xcoach format specification}
        \setMacroInAuxFile{specXcoachDocI}
        First release of the XML specification of the \xcoach format (DTD)
        and its associated documentation allowing to start HLS tools development.
    \itemV{6}{12}{d+x}{\Slip}{\xcoach format specification}
        \setMacroInAuxFile{specXcoachDocII}
        Second release of XML specification of the \xcoach format
        taking into account the corrections and modifications that the
        developers of HAS tools suggested.
    \itemL{12}{18}{d+x}{\Slip}{\xcoach format specification}{7:3:0}
        \setMacroInAuxFile{specXcoachDoc}
        Last release of XML specification of the \xcoach format enhanced with
        the expression of loop potential parallelism.
%
    \itemV{6}{12}{x}{\Subs}{C2X tool}
        \setMacroInAuxFile{specXcoachToCAI}
        This deliverable groups 2 tools.
        The first one C2X is a GCC plugin that generates a \xcoach description
        (defined in {\specXcoachDocI} deliverable) from a C/C++ task description.
        The second one X2C regenerates a C description from a \xcoach description.
    \itemL{12}{18}{x}{\Subs}{C2X tool}{4:2:0}
        \setMacroInAuxFile{specXcoachToCA}
         An updated version of C2X and X2C (\specXcoachToCAI) which supports the
         \xcoach format defined in the {\specXcoachDoc} deliverable.
%
    \itemV{12}{18}{x}{\Supmc}{First release of X2SC}
        \setMacroInAuxFile{specXcoachToSystemCI}
        The first release of the software tool X2SC  that translates \xcoachplus
        description to CABA and TLM-DT SystemC module.
    \itemL{18}{24}{x}{\Supmc}{X2SC tool}{0:2:0}
        \setMacroInAuxFile{specXcoachToSystemC}
        Final release of the former software (\specXcoachToSystemCI).
    \itemV{12}{18}{x}{\Subs}{First release of the X2VHDL}
        \setMacroInAuxFile{specXcoachToVhdlI}
        The first release of the software tool X2VHDL that translates \xcoachplus
        description to synthesizable VHDL description.
    \itemL{18}{24}{x}{\Subs}{X2VHDL tool}{0:3:0}
        \setMacroInAuxFile{specXcoachToVhdl}
        Final release of the former software (\specXcoachToVhdlI).
    \end{livrable}
%
\subtask{Tool for cell library creation}
    Back-end HLS tools use a characterized macro-cell library to build the
    micro-architecture of a coprocessor. The characterization of a cell depends
    on the target device. The role of this \ST is to define the macro-cells and
    to provide a tool that characterizes them automatically by synthesizing them
    and by extracting their delays. This is done by using RTL synthesis.
    \begin{livrable}
    \itemL{0}{6}{d}{\Subs}{Macro-cell definition}{1:0:0}
        \setMacroInAuxFile{specMacroCell}
        Definition of the macro cells and the file format describing them.
    \itemL{6}{12}{x}{\Subs}{Macro-cell library generator}{2:0:0}
        Final release of the software tool that generates automatically the
        characterized macro-cell library for a FPGA device.
    \end{livrable}
\end{workpackage}