1 | \begin{taskinfo} |
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2 | \let\UPMC\leader |
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3 | \let\ALL\enable |
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4 | \end{taskinfo} |
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5 | % |
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6 | \begin{objectif} |
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7 | The objectives of this task are the specification of the designer input, the |
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8 | definition of the hardware architectural templates and of all the features |
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9 | that the HAS tools will share. |
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10 | An other objective is the specification of the framework used to facilitate the |
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11 | exploitation and the integration of the core engine into an industrial flow. |
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12 | \end{objectif} |
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13 | % |
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14 | \begin{workpackage} |
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15 | \subtask{Specification of the COACH environment} |
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16 | This \ST specifies the global COACH environment for the system designer: |
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17 | the core engine which is seen as a black box associated |
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18 | with a configuration framework based on Eclipse. |
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19 | This framework will be integrated into Magillem tool suite. |
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20 | The deliverables specify |
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21 | how to feed COACH (the inputs), |
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22 | how to use COACH (use model), |
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23 | what is generated (the outputs) |
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24 | and how the Magillem framework interacts with the core engine. |
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25 | \begin{livrable} |
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26 | \itemV{0}{6}{d}{\Supmc}{Use model specification} |
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27 | This document describes the use model of COACH. It will be a cooperative work. |
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28 | Its main parts are: |
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29 | \begin{description} |
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30 | \item[General overview] (\Supmc) |
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31 | \item[CSG specification] (\Stima): |
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32 | here the COACH System Generator is specified: |
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33 | how the task graph is described, the communication schemes and |
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34 | its associated API (Application Programming Interface). |
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35 | The base is the SRL library and the MWMR communication component defined |
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36 | by the SocLib ANR project. |
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37 | Nevertheless, these basic schemes will be enhanced to allow more efficient |
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38 | synthesis. |
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39 | \item[HAS specification] (\Subs): |
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40 | this part focuses on the Hardware Accelerator Synthesis. |
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41 | It specifies how tasks must be written (C/C++ subset) and how |
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42 | communication schemes must be described for coprocessor synthesis. |
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43 | \item[Magillem framework specification] (\Smds): |
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44 | this part specifies the functionalities enabling the interactions between |
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45 | Magillem and the core engine. |
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46 | \end{description} |
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47 | \itemL{6}{12}{d}{\Supmc}{Use model specification}{2:0:0} |
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48 | \setMacroInAuxFile{useModelSpecification} |
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49 | The final version of the Use model specification enhanced |
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50 | with the feed-backs of the demonstrator \STs. |
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51 | \OtherPartner{0}{12}{\Slip} {1:0:0} |
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52 | \OtherPartner{0}{12}{\Sinria} {1:0:0} |
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53 | \OtherPartner{0}{12}{\Stima} {2:0:0} |
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54 | \OtherPartner{0}{12}{\Subs} {2:0:0} |
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55 | \OtherPartner{0}{12}{\Sbull} {1:0:0} |
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56 | \OtherPartner{0}{12}{\Sthales}{1:0:0} |
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57 | \OtherPartner{0}{12}{\Smds} {2:0:0} |
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58 | \end{livrable} |
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59 | % |
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60 | \subtask{Internal software structure} |
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61 | \begin{livrable} |
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62 | \itemL{0}{6}{d}{\Supmc}{COACH internal \ganttlf software architecture}{1:0:0} |
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63 | \OtherPartner{0}{6}{\Stima} {.5:0:0} |
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64 | This document lists all the COACH software components and how they cooperate. |
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65 | It will refine the software architecture presented in |
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66 | Figures~\ref{archi-hls} and~\ref{archi-hpc}. |
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67 | \end{livrable} |
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68 | % |
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69 | \subtask{\xcoach format} |
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70 | This \ST specifies the \xcoach and the \xcoachplus formats. |
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71 | \begin{livrable} |
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72 | \itemV{0}{6}{d+x}{\Slip}{\xcoach format specification} |
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73 | \setMacroInAuxFile{specXcoachDocI} |
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74 | First release of the XML specification of the \xcoach format (DTD) |
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75 | and its associated documentation allowing to start HLS tools development. |
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76 | \itemV{6}{12}{d+x}{\Slip}{\xcoach format specification} |
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77 | \setMacroInAuxFile{specXcoachDocII} |
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78 | Second release of XML specification of the \xcoach format |
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79 | taking into account the corrections and modifications that the |
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80 | developers of HAS tools suggested. |
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81 | \itemL{12}{18}{d+x}{\Slip}{\xcoach format specification}{4:2:0} |
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82 | \OtherPartner{0}{18}{\Supmc} {.5:.5:0} |
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83 | \OtherPartner{0}{18}{\Stima} {.5:.5:0} |
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84 | \OtherPartner{0}{18}{\Sinria} {.5:.5:0} |
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85 | \setMacroInAuxFile{specXcoachDoc} |
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86 | Last release of XML specification of the \xcoach format enhanced with |
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87 | the expression of loop potential parallelism. |
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88 | % |
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89 | \itemV{6}{12}{x}{\Subs}{C2X tool} |
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90 | \setMacroInAuxFile{specXcoachToCAI} |
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91 | This deliverable groups 2 tools. |
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92 | The first one C2X is a GCC plugin that generates a \xcoach description |
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93 | (defined in {\specXcoachDocI} deliverable) from a C/C++ task description. |
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94 | The second one X2C regenerates a C description from a \xcoach description. |
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95 | \itemL{12}{18}{x}{\Subs}{C2X tool}{4:2:0} |
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96 | \setMacroInAuxFile{specXcoachToCA} |
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97 | An updated version of C2X and X2C (\specXcoachToCAI) which supports the |
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98 | \xcoach format defined in the {\specXcoachDoc} deliverable. |
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99 | % |
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100 | \itemV{12}{18}{x}{\Supmc}{First release of X2SC} |
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101 | \setMacroInAuxFile{specXcoachToSystemCI} |
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102 | The first release of the software tool X2SC that translates \xcoachplus |
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103 | description to CABA and TLM-DT SystemC module. |
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104 | \itemL{18}{27}{x}{\Supmc}{X2SC tool}{0:1:.5} |
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105 | \setMacroInAuxFile{specXcoachToSystemC} |
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106 | Final release of the former software (\specXcoachToSystemCI). |
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107 | \itemV{12}{18}{x}{\Subs}{First release of the X2VHDL} |
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108 | \setMacroInAuxFile{specXcoachToVhdlI} |
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109 | The first release of the software tool X2VHDL that translates \xcoachplus |
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110 | description to synthesizable VHDL description. |
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111 | \itemL{18}{27}{x}{\Subs}{X2VHDL tool}{0:3:2} |
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112 | \setMacroInAuxFile{specXcoachToVhdl} |
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113 | Final release of the former software (\specXcoachToVhdlI). |
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114 | \end{livrable} |
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115 | % |
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116 | \subtask{Tool for cell library creation} |
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117 | Back-end HLS tools use a characterized macro-cell library to build the |
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118 | micro-architecture of a coprocessor. The characterization of a cell depends |
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119 | on the target device. The role of this \ST is to define the macro-cells and |
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120 | to provide a tool that characterizes them automatically by synthesizing them |
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121 | and by extracting their delays. This is done by using RTL synthesis. |
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122 | \begin{livrable} |
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123 | \itemL{0}{6}{d}{\Subs}{Macro-cell definition}{2:0:0} |
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124 | \OtherPartner{0}{6}{\Supmc} {.5:0:0} |
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125 | \OtherPartner{0}{6}{\Stima} {.5:0:0} |
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126 | \setMacroInAuxFile{specMacroCell} |
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127 | Definition of the macro cells and the file format describing them. |
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128 | \itemL{6}{12}{x}{\Subs}{Macro-cell library generator}{2:0:0} |
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129 | Final release of the software tool that generates automatically the |
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130 | characterized macro-cell library for a FPGA device. |
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131 | \end{livrable} |
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132 | \end{workpackage} |
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