source: anr/task-backend.tex @ 384

Last change on this file since 384 was 356, checked in by coach, 14 years ago

1ere Pre-release

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[291]1\begin{taskinfo}
2\let\UBS\leader
3\let\UPMC\enable
4\let\TIMA\enable
5\end{taskinfo}
6%
7\begin{objectif}
8The objectives of this task are to provide two HAS back-ends and
9a tool that adapt the coprocessor frequency to the FPGA-SoC frequency as required
10by the processors and the system bus.
11\\
12The HAS back-ends as shown in figure~\ref{archi-hls} reads an \xcoach
13description and provides an \xcoachplus description (a \xcoach description
14annotated with hardware information such as variables binding to registers,
15operations bindings to cells/functional units).
16%The \xcoach format being generated by the \novers{\specXcoachToCA} deliverable
17%and the \xcoachplus being treated by the \novers{\specXcoachToSystemC} and the
18%\novers{\specXcoachToVhdl} deliverables, this task strongly depends on task~1.
19\par
20For the two HAS front-end, this task is based on the already existing HLS tools GAUT and
21UGH. These tools \textbf{are complementary and not in competition} because they
22cover respectively data and control dominated designs.
23\end{objectif}
[356]24%
[291]25\begin{workpackage}
26\subtask{Integration of UGH \& GAUT HLS tools to COACH}
27    This adaptation will be done incrementally in three steps:
28    \begin{enumerate}
[295]29      \item Make tools to read \xcoach format defined in {\NOVERSspecXcoachDoc} deliverable.
[291]30      \item Make tools to recognize the API of task communication defined in
[295]31        {\NOVERSuseModelSpecification} deliverable.
[291]32      \item Make tools to write \xcoachplus format to let
[295]33        {\NOVERSspecXcoachToSystemC} deliverable generate the SystemC model and
34        {\NOVERSspecXcoachToVhdl} deliverable generate the synthesizable VHDL description.
[291]35    \end{enumerate}
36    \begin{livrable}
37    \itemV{6}{12}{x}{\Stima}{UGH integration}
38        UGH release that reads \xcoach format.
39    \itemV{12}{18}{x}{\Stima}{UGH integration}
40        UGH release that interprets the task communication API.
[304]41    \itemV{18}{27}{x}{\Supmc}{UGH integration}
[291]42        UGH release that writes \xcoachplus format.
[304]43    \itemL{27}{36}{x}{\Stima}{UGH integration}{3:3:1}
44        \OtherPartner{0}{12}{\Supmc}{1:2.5:1}
[291]45        UGH release taking into account demonstrator's feedback.
46%
47    \itemV{6}{12}{x}{\Subs}{GAUT integration}
48        GAUT release that reads \xcoach format.
49    \itemV{12}{18}{x}{\Subs}{GAUT integration}
50        GAUT release that interprets the task communication API.
[304]51    \itemV{18}{27}{x}{\Subs}{GAUT integration}
[291]52        GAUT release that writes \xcoachplus format.
[342]53    \itemL{27}{36}{x}{\Subs}{GAUT integration}{7:6:3}
[291]54        \setMacroInAuxFile{gautFinal}
55        GAUT release taking into account demonstrator's feedback.
56    \end{livrable}
57%
58\subtask{Coprocessor frequency adaptation}
59    In FPGA-SoC, the frequency is given by the processor(s) and the system BUS. The coprocessors
60    generated by HLS synthesis must respect this frequency. However, the HLS tools can not
61    guarantee that the micro-architectures they generate accurately respect this
62    frequency. This is especially the case when the target is a FPGA device, because the
63    delays are really known only after the RTL synthesis and that estimated delays used
64    by the HLS are very inaccurate. The goal of this \ST is to provide a tool that adapts
65    the coprocessors frequency to the FPGA-SoC frequency after the coprocessor RTL
66    synthesis.
67    \begin{livrable}
68    \itemV{0}{12}{d}{\Supmc}{Frequency calibration}
69        A document describing the set up of the coprocessor frequency calibration.
[304]70    \itemV{12}{27}{x}{\Supmc}{Frequency calibration}
[291]71        A VHDL description of hardware added to the coprocessor to enable the calibration.
[304]72    \itemL{27}{33}{x}{\Supmc}{Frequency calibration}{1:1:4}
[291]73        \setMacroInAuxFile{freqCalibrationVhdl}
74        The frequency calibration software consists of a driver in the FPGA-SoC operating
75        system and of a control software.
76    \end{livrable}
77%
78\subtask{GAUT enhancement}
79    \begin{livrable}
[304]80    \itemV{18}{27}{d}{\Subs}{GAUT enhancement}
[291]81        Specification of GAUT enhancements.
82        The first ones is to support new constraints and objectives.
83        The second one is a Design Space Exploration framework, GAUT will be
84        able to use synthesis feed-back informations in order to explore the
85        design space and to generate optimized architectures.
[342]86    \itemL{27}{36}{x}{\Subs}{GAUT enhancement}{0:5:4}
[291]87        Integration of these enhancements into the final GAUT release
88        ({\gautFinal} deliverable).
89    \end{livrable}
90\end{workpackage}
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