source: anr/task-csg.tex @ 302

\begin{taskinfo}
\let\UPMC\leader
\let\TIMA\enable
\end{taskinfo}
%
\begin{objectif}
The objectives of this task are to allow the system designer to explore the
design space by quickly prototyping and then to automatically generate the
FPGA-SoC systems.  It is described on figure~\ref{archi-csg} and it consists of:
\begin{itemize}
  \item The development of the synthesizable models required for the connection
        of the coprocessors on the platform bus (2 bridges).
  \item The configuration and the development of drivers of the operating
        systems (Board Support Package, HAL).
  \item The CSG software that generates the SystemC simulators for prototyping
        and the FPGA-SoC system including its bitstream and software executable code.
\end{itemize}
A first release will be delivered at $T0+12$ to allow the demonstrators to start working.
This release will include the standard communication schemes based on SoCLib MWMR component
and support the neutral architectural template for prototyping and hardware generation.
\end{objectif}
%
\begin{workpackage}
\subtask{Bridge implementation}
    This \ST deals with the development of the synthesizable models required for
        the connection of the coprocessors on the platform bus.
    \begin{livrable}
    \itemL{18}{30}{h}{\Stima}{HPC hardware \xilinx}{0:2:5}
        \setMacroInAuxFile{hpcPlbBridge}
        The synthesizable VHDL description of a PLB/VCI bridge.
    \itemL{18}{30}{h}{\Supmc}{HPC hardware \altera}{0:2:5}
        \setMacroInAuxFile{hpcAvalonBridge}
        The synthesizable VHDL description of an AVALON/VCI bridge.
    \end{livrable}
\subtask{OS setup}
        This \ST consists of the configuration of the SocLib DNA operating
    system and the development of drivers for the hardware architectural templates.
    For the \altera and \xilinx architectural templates, the OS must also be ported on
    the NIOS2 and MICROBLAZE processors.
    \begin{livrable}
    \itemV{6}{8}{x}{\Stima}{DNA OS}
        The drivers required for the first CSG milestone.
    \itemV{8}{18}{x}{\Stima}{DNA 0S}
        The drivers required for the second CSG milestone.
    \itemL{18}{33}{x}{\Stima}{DNA OS drivers for SoCLib}{6:2:2}
        \OtherPartner{6}{33}{\Supmc}  {.5:.5:.5}
        \mustbecompleted{TIMA : ajouter des précisions sur le travail et ce
        que fait upmc}
        Final release of the DNA OS drivers.
    \itemL{12}{18}{x}{\Stima}{Driver ports}{0:2:0}
        \OtherPartner{6}{33}{\Supmc}  {0:2:0}
    \mustbecompleted{TIMA: tima sur Microblaze, UPMC sur Nios}
        Porting of DNA OS on the NIOS2 and MICROBLAZE processors.
    \end{livrable}
\subtask{Implementation of CSG}
    \begin{livrable}
    \itemV{0}{12}{x}{\Supmc}{CSG}
        The first software release of the CSG tool that will allow demonstrators to start
        working by using the neutral architectural template only for SystemC.
    \itemV{12}{18}{x}{\Supmc}{CSG}
        The second release of CSG integrates the VHDL driver for the neutral
        architectural template, and an integration of an HLS tools
        but only for SystemC prototyping.
    \itemV{18}{24}{x}{\Supmc}{CSG}
        This release extends CSG to FPGA-SoC generation for the \xilinx and
                \altera architectural template.
    \itemL{24}{36}{x}{\Supmc}{CSG tool}{5:3:2}
        \OtherPartner{0}{36}{\Stima}{0:6:0}
        \OtherPartner{0}{36}{\Smds}{0:6:0}
                \setMacroInAuxFile{csgImplementation}
        \mustbecompleted{TIMA : integration d'OS dans CSG, en particulier DNA}
        Final release of CSG enhanced by the demonstrator's feedback.
    \end{livrable}
\end{workpackage}