source: anr/task-csg.tex @ 293

Last change on this file since 293 was 291, checked in by coach, 14 years ago

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1\begin{taskinfo}
2\let\UPMC\leader
3\let\TIMA\enable
4\end{taskinfo}
5%
6\begin{objectif}
7The objectives of this task are to allow the system designer to explore the
8design space by quickly prototyping and then to automatically generate the
9FPGA-SoC systems.  It is described on figure~\ref{archi-csg} and it consists of:
10\begin{itemize}
11  \item The development of the synthesizable models required for the connection
12        of the coprocessors on the platform bus (2 bridges).
13  \item The configuration and the development of drivers of the operating
14        systems (Board Support Package, HAL).
15  \item The CSG software that generates the SystemC simulators for prototyping
16        and the FPGA-SoC system including its bitstream and software executable code.
17\end{itemize}
18A first release will be delivered at $T0+12$ to allow the demonstrators to start working.
19This release will include the standard communication schemes based on SoCLib MWMR component
20and support the neutral architectural template for prototyping and hardware generation.
21\end{objectif}
22%
23\begin{workpackage}
24\subtask{Bridge implementation}
25    This \ST deals with the development of the synthesizable models required for
26        the connection of the coprocessors on the platform bus.
27    \begin{livrable}
28    \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0}
29        \setMacroInAuxFile{hpcPlbBridge}
30        The synthesizable VHDL description of a PLB/VCI bridge.
31    \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0}
32        \setMacroInAuxFile{hpcAvalonBridge}
33        The synthesizable VHDL description of an AVALON/VCI bridge.
34    \end{livrable}
35\subtask{OS setup}
36        This \ST consists of the configuration of the SocLib DNA operating
37    system and the development of drivers for the hardware architectural templates.
38    For the \altera and \xilinx architectural templates, the OS must also be ported on
39    the NIOS2 and MICROBLAZE processors.
40    \begin{livrable}
41    \itemV{6}{8}{x}{\Stima}{DNA OS}
42        The drivers required for the first CSG milestone.
43    \itemV{8}{18}{x}{\Stima}{DNA 0S}
44        The drivers required for the second CSG milestone.
45    \itemL{18}{33}{x}{\Stima}{DNA OS drivers}{6:3:2}
46        Final release of the DNA OS drivers.
47    \itemL{6}{18}{x}{\Stima}{Ports of DNA OS}{3:1:0}
48        Porting of DNA OS on the NIOS2 and MICROBLAZE processors.
49    \end{livrable}
50\subtask{Implementation of CSG}
51    \begin{livrable}
52    \itemV{0}{12}{x}{\Supmc}{CSG tool}
53        The first software release of the CSG tool that will allow demonstrators to start
54        working by using the neutral architectural template only for SystemC.
55    \itemV{12}{18}{x}{\Supmc}{CSG}
56        The second release of CSG integrates the VHDL driver for the neutral
57        architectural template, and an integration of an HLS tools
58        but only for SystemC prototyping.
59    \itemV{18}{24}{x}{\Supmc}{CSG}
60        This release extends CSG to FPGA-SoC generation for the \xilinx and
61                \altera architectural template.
62    \itemL{24}{36}{x}{\Supmc}{CSG tool}{6:5.5:5.5}
63                \setMacroInAuxFile{csgImplementation}
64        Final release of CSG enhanced by the demonstrator's feedback.
65    \end{livrable}
66\end{workpackage}
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