source: anr/task-csg.tex @ 348

Last change on this file since 348 was 347, checked in by coach, 14 years ago

minor language modifications

  • Property svn:eol-style set to native
  • Property svn:keywords set to Revision HeadURL Id Date
File size: 4.3 KB
Line 
1\begin{taskinfo}
2\let\UPMC\leader
3\let\TIMA\enable
4\end{taskinfo}
5%
6\begin{objectif}
7The objectives of this task are to allow the system designer to explore the
8design space by quickly prototyping and then to automatically generate the
9FPGA-SoC systems.  It is described on figure~\ref{archi-csg} and it consists of:
10\begin{itemize}
11  \item The development of the synthesizable models required for the connection
12    of the coprocessors on the platform bus (2 bridges).
13  \item The configuration and the development of drivers of the operating
14    systems (Board Support Package, HAL).
15  \item The CSG software that generates the SystemC simulators for prototyping
16    and the FPGA-SoC system including its bitstream and software executable code
17    (see Figures~\ref{archi-csg} and ~\ref{archi-hls}).
18\end{itemize}
19A first release will be delivered at $T0+12$ to allow an early start of demonstrator
20implementations.
21This release will include the standard communication schemes based on SoCLib MWMR component
22and support the neutral architectural template for prototyping and hardware generation.
23\end{objectif}
24%
25\begin{workpackage}
26\subtask{Bridge implementation}
27    This \ST deals with the development of the synthesizable models required for
28    the connection of the coprocessors on the platform bus.
29    \begin{livrable}
30    \itemL{18}{30}{h}{\Stima}{HPC hardware \xilinx}{0:3:3}
31        \setMacroInAuxFile{hpcPlbBridge}
32        The synthesizable VHDL description of a VCI/\xilinxbus bridge.
33    \itemL{18}{30}{h}{\Supmc}{HPC hardware \altera}{0:3:3}
34        \setMacroInAuxFile{hpcAvalonBridge}
35        The synthesizable VHDL description of an VCI/AVALON bridge.
36    \end{livrable}
37\subtask{OS setup}
38    This \ST consists of the configuration of the SocLib DNA operating
39    system and the development of drivers for the hardware architectural templates.
40    For the \altera and \xilinx architectural templates, the OS must also be ported on
41    the NIOS2 and \xilinxcpu processors.
42    \begin{livrable}
43    \itemV{6}{8}{x}{\Stima}{DNA OS}
44        Identification and Specification of the drivers required for
45        the first CSG release using a vendor neutral virtual
46        prototype.
47    \itemV{8}{18}{x}{\Stima}{DNA 0S}
48        Implementation of the identified drivers and integration in
49        the first CSG release.
50    \itemL{18}{33}{x}{\Stima}{DNA OS drivers for SoCLib}{4:2:2}
51        \OtherPartner{6}{33}{\Supmc}  {.5:.5:.5}
52        Final release of the DNA OS drivers for the CSG selected IPs.
53    \itemL{12}{18}{x}{\Stima}{Driver ports}{0:2:0}
54        \OtherPartner{6}{33}{\Supmc}  {0:2:0}
55    %\mustbecompleted{TIMA: tima sur \xilinxcpu, UPMC sur Nios}
56        Final port of the DNA OS on the NIOS2 and \xilinxcpu
57        processors and CSG platforms, along with the driver dependant
58        drivers.
59        \Stima will focus on the platform based on Xilinx IPs, whereas
60        \Supmc will focus on the Altera related IPs and platform.
61    \end{livrable}
62\subtask{Implementation of CSG}
63    \begin{livrable}
64    \itemV{0}{12}{x}{\Supmc}{CSG}
65        The first software release of the CSG tool that will allow demonstrators to start
66        working by using the neutral architectural template only for SystemC.
67    \itemV{12}{18}{x}{\Supmc}{CSG}
68        The second release of CSG integrates the VHDL driver for the neutral
69        architectural template, and an integration of an HLS tools
70        but only for SystemC prototyping.
71    \itemV{18}{27}{x}{\Supmc}{CSG}
72        This release extends CSG to FPGA-SoC generation for the \xilinx and
73        \altera architectural template.
74    \itemL{27}{36}{x}{\Supmc}{CSG tool}{5:2:3}
75        \OtherPartner{0}{36}{\Stima}{1:3:2}
76        \OtherPartner{0}{36}{\Smds}{1:3:3}
77        \setMacroInAuxFile{csgImplementation}
78        Final release of CSG enhanced by the demonstrator's feedback.
79        \\
80        The work will be split between the partner as follow: 1) \Supmc will
81        design the core of CSG, 2) \Stima will design the part concerning the
82        generation of system software and the configuration of CSG to other OS.
83        3) \Smds will focus on interfacing CSG to the IP-XACT format for
84        generating IP integrable into a IP-XACT flow such as the one defined in the SoCket project and to
85        configure CSG to new IP or plate-form.
86    \end{livrable}
87\end{workpackage}
Note: See TracBrowser for help on using the repository browser.