source: anr/task-frontend.tex @ 385

Last change on this file since 385 was 367, checked in by coach, 14 years ago

LIP

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1\begin{taskinfo}
2\let\LIP\leader
3\let\INRIA\enable
4\let\UBS\enable
5\let\UPMC\enable
6\let\TIMA\enable
7\end{taskinfo}
8%
9\begin{objectif}
10The objective of this task is to convert the input specification of
11an hardware accelerator, which must be written in a familiar language
12(C/C++) with as few constraints as possible, into a form suitable for
13the HLS tools (i.e. HAS back-end tools of the COACH project). If the
14target is an ASIP, the front-end has to extract
15patterns from the source code and convert them into the definition
16of an extensible processor. If the target is a process network, the
17front end has to distribute the workload and the data sets as fairly
18as possible, identify communication channels, and output an \xcoach
19description.
20\end{objectif}
21%
22\begin{workpackage}
23  \subtask{ASIP compiler}
24  This sub-task aims at providing compiler support for custom instructions
25  within the HAS front-end. It will take as input the COACH intermediate
26  representation, and will output an annotated COACH IR containing the custom
27  instructions definitions along with their occurrence in the application.
28    \begin{livrable}
29      \itemV{0}{12}{x}{\Sinria}{ASIP compilation flow}
30        In this first version of the software, the computations patterns corresponding to
31        custom instructions are specified by the user, and then automatically extracted (when
32        beneficial) from the application intermediate representation.
33      \itemL{12}{27}{x}{\Sinria}{ASIP compilation flow}{6:6:3}
34        In this second version, the software will also be able to automatically identify
35        interesting pattern candidates in the application code, and use them as custom
36        instructions. 
37    \end{livrable}
38%
39 \subtask{Micro-architectural template models for ASIP}
40 In this sub-task, we provide micro-architectural template models for the two target
41 processor architectures (NIOS-II and MIPS) supported within the COACH-ASIP design flow.
42 For each processor, we provide a simulation model (System-C) and a synthesizable model (VHDL)
43 of the architecture, along with its architectural extensions
44    \begin{livrable}
45      \itemV{0}{12}{x}{\Sinria}{SystemC for extensible MIPS }
46      { A SystemC simulation model for a simple extensible MIPS architectural template }
47      \itemL{12}{27}{x}{\Sinria}{SystemC for extensible MIPS}{3:2:1}
48      {A SystemC simulation model for an extensible MIPS with a tight architectural integration of
49      its instruction set extensions}
50      \itemV{3}{18}{h}{\Sinria}{VHDL for an extensible MIPS}
51      {A synthesizable VHDL model for a simple extensible MIPS architectural template}
52      \itemL{18}{27}{h}{\Sinria}{VHDL for extensible MIPS}{8:8.5:3}
53      {A synthesizable VHDL model for an extensible MIPS with a tight architectural integration of
54      its instruction set extensions}
55      \itemL{27}{36}{d}{\Sinria}{Evaluation report }{0:0:3}
56      {An evaluation report with quantitative analysis of the performance/area trade-off induced by
57      the different approaches}
58    \end{livrable}
59%
60 \subtask{Automatic parallelization and memory optimization}
61 This sub-task aims at providing a source-level optimizer in front the
62 HLS back-end tools. The optimizations are threefold:
63    \begin{itemize}
64    \item Extraction of parallelism in polyhedral loops and conversion
65      into a process network.
66    \item Minimization of intra-process local memory
67    \item Construction of inter-process FIFOs
68    \end{itemize}
69    We will design these methods by using polyhedral techniques, as we did
70    in the past for pure HPC optimizations. The program model is typically
71    regular programs where loop bounds, conditions and array indices are
72    affine functions. In a second part, we will extend the program model
73    by using conservative approximations.
74   \begin{livrable}
75    \itemV{0}{6}{d}{\Slip}{Method, Preliminary Definition}
76      Description and specification of a process construction method for programs with
77      polyhedral loops.
78    \itemV{6}{12}{x}{\Slip}{Process construction}
79      Preliminary implementation in the Syntol framework.
80      At this step the software will just implement a single constructor.
81    \itemL{30}{36}{d+x}{\Slip}{Process generation method}{3:0:3}
82      Final assessment of the method and improved version of the specification.
83%
84    \itemV{6}{12}{d}{\Slip} {Arrays and FIFO}
85    Description and specification of the FIFO construction method
86    and the local memory optimization method.
87    \itemV{12}{18}{d+x}{\Slip} {Arrays and FIFO}
88    Preliminary implementation in the Bee framework.
89    Conversion of the input and output of Bee to the \xcoach format.
90    At this step, only local memory optimization will be available.
91    \itemL{18}{30}{d+x}{\Slip}{Arrays and FIFO}{1.5:2.0:1}
92    Final assessment of the method and improved version of the specification.
93%
94    \itemV{18}{30}{d+x}{\Slip}{Non-polyhedral extension}
95      Extension of automatic parallelization and memory optimization
96      to non-polyhedral loops. Implementation in the Bee framework.
97    \itemL{30}{36}{d+x}{\Slip} {Non-polyhedral extension}{0.0:9.0:13.0}
98      Final release taking into account the feedbacks from the
99      demonstrator \STs.
100   \end{livrable}
101%
102\end{workpackage}
103   
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