source: anr/task-hpc.tex @ 322

Last change on this file since 322 was 309, checked in by coach, 14 years ago

Fixed Bull data

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  • Property svn:keywords set to Revision HeadURL Id Date
File size: 5.2 KB
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1% vim:set spell:
2% vim:spell spelllang=en:
3
4\begin{taskinfo}
5\let\BULL\leader
6\let\UPMC\enable
7\let\TIMA\enable
8\let\THALES\enable
9\let\XILINX\enable
10\end{taskinfo}
11%
12\begin{objectif}
13This task deals with the COACH HPC feature that consists in accelerating an existing
14application running on a PC by migrating critical parts into a SoC implemented on an
15FPGA plugged to the PC PCI/X bus (figures~\ref{coach-flow} and \ref{archi-hpc}).
16It consists in:
17\begin{itemize}
18\item Specifying and implementing the communication schemes between the software
19  part running on the PC and the FPGA-SoC.
20\item Providing a performance analysis tool helping user in the HPC partitioning
21  (figure~\ref{archi-hpc}).
22\item Providing support for configuration of the FPGA in order to set up the HPC environment.
23\end{itemize}
24The low level hardware transmission support will be the PCI/X bus which allows high bit-rate
25transfers. The reasons of this choice are that both \altera and \xilinx provide PCI/X IP for
26their FPGA and that GPU HPC softwares use also it.
27%This will allow us at least to be inspired by GPU communication schemes and may be to reuse
28%parts of the GPU softwares.
29\end{objectif}
30%
31\begin{workpackage}
32  \subtask{Implementation of API between PC and FPGA-SoC}
33    \begin{livrable}
34      \itemL{0}{6}{d}{\Sbull}{HPC communication API}{3:0:0}
35        \OtherPartner{0}{6}{\Supmc}{.5:0:0}
36        \OtherPartner{0}{6}{\Stima}{.5:0:0}
37        \setMacroInAuxFile{hpcCommApi}
38        Specification of the API.
39      \itemL{6}{12}{x}{\Supmc}{HPC partitioning helper}{1:0:0}
40        \setMacroInAuxFile{hpcCommHelper}
41        A library implementing the communication API defined in the {\hpcCommApi} deliverable.
42        This library is dedicated to help the end-user to partition an application for HPC.
43      \itemL{21}{27}{x}{\Stima}{HPC API for Linux}{0:2:1.5}
44        \OtherPartner{21}{27}{\Supmc}{0:1.5:1.0}
45        \OtherPartner{21}{27}{\Sbull}{0:0.0:0.5}
46        \setMacroInAuxFile{hpcForLinux}
47        This deliverable groups all the software components to implement the
48        HPC communication API (\NOVERShpcCommApi).
49        \Supmc will develop the Linux part (a C library and a LINUX module),
50        \Stima will develop the FPGA-SoC part (a DNA driver),
51        \Sbull will check this implementation on its demonstrator (\NOVERSbullAppSpecification).
52    \end{livrable}
53%
54\subtask{SystemC model of the PCI/X}
55    This \ST deals with the implementation of SystemC modules
56    required by the neutral architectural template for using the PCI/X IP of \altera and \xilinx.
57    \begin{livrable}
58    \itemL{21}{27}{h}{\Supmc}{PCI/X traffic generator}{0:1:1}
59        The SystemC description of a component that generates PCI/X traffic. It is
60        required to prototype FPGA-SoC dedicated to HPC.
61    \end{livrable}
62%
63\subtask{HPC environment set up}
64% It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library.
65     \begin{livrable}
66     \itemL{18}{36}{x}{\Stima}{Support for HPC environment set up}{0:4:4}
67      Modification of the CSG software to set-up the HPC environment.
68      The objective is to run easily HPC application and the main features are:
69      automatic calibration of coprocessors (\freqCalibrationVhdl), automatic download of
70      SoC on FPGA (bitstream and application loader), starting the PC and FPGA
71      part of the HPC application.
72     \end{livrable}
73%     \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:4:12}
74%       This livrable is a CSG module allowing to partition the task graph along
75%       the dynamic partial reconfiguration regions. The resulting task-region assignement
76%       is directly used for generation of bitstreams. The module also produces reconfiguration
77%       management software to be run on the SoC-FPGA.
78%     \itemL{18}{30}{x}{\Stima}{Dynamic reconfiguration \ganttlf for DNA drivers}{0:3:3}
79%         \setMacroInAuxFile{hpcDynconfDriver}
80%       The drivers required by the DNA OS in order to manage dynamic partial
81%         reconfiguration inside the SoC-FPGA.
82%     \itemL{30}{36}{x}{\Supmc}{Dynamic reconfiguration \ganttlf for  MUTEKH drivers}{0:0:1}
83%         Port of the {\hpcDynconfDriver} drivers on the MUTEKH OS.
84%     \itemL{24}{36}{x}{\Stima}{Profiler for \ganttlf dynamic reconfiguration}{0:0:6}
85%         Extension of the HPC partionning helper in order to integrate dynamic partial
86%         reconfiguration dedicated features (reconfiguration time of regions, variable
87%         number of coprocessors).
88%     \itemL{24}{36}{d}{\Sxilinx}{Optimisation for \xilinx \ganttlf dynamic reconfiguration}{0:0:2}
89%         \xilinx will work with \tima in order to better take into account during
90%         partitioning decisions specific constraints due to partial reconfiguration process.
91%         The deliverable is a document describing the \xilinx specific constraints.
92%     \end{livrable}
93% %\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
94% %   with its PCI/X IP. These boards are dedicated to the COACH HPC development.
95% %   They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
96% %   \begin{livrable}
97% %   \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards.
98\end{workpackage}
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