source: anr/task-hpc.tex @ 317

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\begin{taskinfo}
\let\BULL\leader
\let\UPMC\enable
\let\TIMA\enable
\let\THALES\enable
\let\XILINX\enable
\end{taskinfo}
%
\begin{objectif}
This task deals with the COACH HPC feature that consists in accelerating an existing
application running on a PC by migrating critical parts into a SoC implemented on an
FPGA plugged to the PC PCI/X bus (figures~\ref{coach-flow} and \ref{archi-hpc}).
It consists in:
\begin{itemize}
\item Specifying and implementing the communication schemes between the software
  part running on the PC and the FPGA-SoC.
\item Providing a performance analysis tool helping user in the HPC partitioning
  (figure~\ref{archi-hpc}).
\item Providing support for configuration of the FPGA in order to set up the HPC environment.
\end{itemize}
The low level hardware transmission support will be the PCI/X bus which allows high bit-rate
transfers. The reasons of this choice are that both \altera and \xilinx provide PCI/X IP for
their FPGA and that GPU HPC softwares use also it.
%This will allow us at least to be inspired by GPU communication schemes and may be to reuse
%parts of the GPU softwares.
\end{objectif}
%
\begin{workpackage}
  \subtask{Implementation of API between PC and FPGA-SoC}
    \begin{livrable}
      \itemL{0}{6}{d}{\Sbull}{HPC communication API}{3:0:0}
        \OtherPartner{0}{6}{\Supmc}{.5:0:0}
        \OtherPartner{0}{6}{\Stima}{.5:0:0}
        \setMacroInAuxFile{hpcCommApi}
        Specification of the API.
      \itemL{6}{12}{x}{\Supmc}{HPC partitioning helper}{1:0:0}
        \setMacroInAuxFile{hpcCommHelper}
        A library implementing the communication API defined in the {\hpcCommApi} deliverable.
        This library is dedicated to help the end-user to partition an application for HPC.
      \itemL{21}{27}{x}{\Stima}{HPC API for Linux}{0:2:1.5}
        \OtherPartner{21}{27}{\Supmc}{0:1.5:1.0}
        \OtherPartner{21}{27}{\Sbull}{0:0.0:0.5}
        \setMacroInAuxFile{hpcForLinux}
        This deliverable groups all the software components to implement the
        HPC communication API (\NOVERShpcCommApi).
        \Supmc will develop the Linux part (a C library and a LINUX module),
        \Stima will develop the FPGA-SoC part (a DNA driver),
        \Sbull will check this implementation on its demonstrator (\NOVERSbullAppSpecification).
    \end{livrable}
%
\subtask{SystemC model of the PCI/X}
    This \ST deals with the implementation of SystemC modules
    required by the neutral architectural template for using the PCI/X IP of \altera and \xilinx.
    \begin{livrable}
    \itemL{21}{27}{h}{\Supmc}{PCI/X traffic generator}{0:1:1}
        The SystemC description of a component that generates PCI/X traffic. It is
        required to prototype FPGA-SoC dedicated to HPC.
    \end{livrable}
%
\subtask{HPC environment set up}
% It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library.
     \begin{livrable}
     \itemL{18}{36}{x}{\Stima}{Support for HPC environment set up}{0:4:4}
      Modification of the CSG software to set-up the HPC environment.
      The objective is to run easily HPC application and the main features are:
      automatic calibration of coprocessors (\freqCalibrationVhdl), automatic download of
      SoC on FPGA (bitstream and application loader), starting the PC and FPGA
      part of the HPC application.
     \end{livrable}
%     \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:4:12}
%       This livrable is a CSG module allowing to partition the task graph along
%       the dynamic partial reconfiguration regions. The resulting task-region assignement
%       is directly used for generation of bitstreams. The module also produces reconfiguration
%       management software to be run on the SoC-FPGA.
%     \itemL{18}{30}{x}{\Stima}{Dynamic reconfiguration \ganttlf for DNA drivers}{0:3:3}
%         \setMacroInAuxFile{hpcDynconfDriver}
%       The drivers required by the DNA OS in order to manage dynamic partial
%         reconfiguration inside the SoC-FPGA.
%     \itemL{30}{36}{x}{\Supmc}{Dynamic reconfiguration \ganttlf for  MUTEKH drivers}{0:0:1}
%         Port of the {\hpcDynconfDriver} drivers on the MUTEKH OS.
%     \itemL{24}{36}{x}{\Stima}{Profiler for \ganttlf dynamic reconfiguration}{0:0:6}
%         Extension of the HPC partionning helper in order to integrate dynamic partial
%         reconfiguration dedicated features (reconfiguration time of regions, variable
%         number of coprocessors).
%     \itemL{24}{36}{d}{\Sxilinx}{Optimisation for \xilinx \ganttlf dynamic reconfiguration}{0:0:2}
%         \xilinx will work with \tima in order to better take into account during
%         partitioning decisions specific constraints due to partial reconfiguration process.
%         The deliverable is a document describing the \xilinx specific constraints.
%     \end{livrable}
% %\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
% %   with its PCI/X IP. These boards are dedicated to the COACH HPC development.
% %   They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
% %   \begin{livrable}
% %   \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards.
\end{workpackage}