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/anr/anr.tex
r3 r1 10 10 \usepackage{xmpmulti} 11 11 \usepackage{graphicx} 12 \usepackage{color}13 14 \definecolor{gris25}{gray}{0.75}15 \definecolor{gris75}{gray}{0.30}16 12 17 13 \title{% 18 14 \textbf{COACH:} 19 15 \textbf{C}onception d'\textbf{A}rchitecture par 20 \textbf{C}ompilation et synt\textbf{H} ï¿œse16 \textbf{C}ompilation et synt\textbf{H}èse 21 17 } 22 18 -
/anr/body.tex
r3 r1 2 2 \hspace{2cm}\begin{scriptsize}\begin{verbatim} 3 3 % 1. CONTEXTE ET POSITIONNEMENT DU PROJET 4 % (1 page maximum) Pr ï¿œsentation gï¿œnï¿œrale du problï¿œme qu'il est proposï¿œde traiter4 % (1 page maximum) Présentation générale du problème qu'il est proposé de traiter 5 5 % dans le projet et du cadre de travail (recherche fondamentale, industrielle ou 6 % d ï¿œveloppement expï¿œrimental).6 % développement expérimental). 7 7 \end{verbatim} 8 8 \end{scriptsize} … … 19 19 due to the design and fabrication costs. 20 20 Nowadays Field Programmable Gate Arrays (FPGA), like Virtex5 from Xilinx and Stratix4 from Altera, 21 can implement a SoC with multiple processors and several coprocessors for less than 10K euros 22 per item. In addition, High Level Synthesis (HLS) becomes more mature and allows to automate23 design and to drastically decrease its cost in terms of man power. Thus, both FPGA and HLS24 tend to spread overHPC for small companies targeting low volume markets.21 can implement a SoC with multiple processors and several coprocessors for less than 10K euros the piece. 22 In addition, High Level Synthesis (HLS) becomes more mature and allows to automize design 23 and to decrease drastically its cost in terms of man power. Thus, both FPGA and HLS tends to spread over 24 HPC for small companies targeting low volume markets. 25 25 \par 26 26 To get an efficient embedded system, designer has to take into account application characteristics when it … … 75 75 % 1.1. CONTEXTE ET ENJEUX ECONOMIQUES ET SOCIETAUX 76 76 % (2 pages maximum) 77 % D ï¿œcrire le contexte ï¿œconomique, social, rï¿œglementaire. dans lequel se situe78 % le projet en pr ï¿œsentant une analyse des enjeux sociaux, ï¿œconomiques, environnementaux,79 % industriels. Donner si possible des arguments chiffr ï¿œs, par exemple, pertinence et80 % port ï¿œe du projet par rapport ï¿œ la demande ï¿œconomique (analyse du marchï¿œ, analyse des81 % tendances), analyse de la concurrence, indicateurs de r ï¿œduction de coï¿œts, perspectives82 % de march ï¿œs (champs d'application, .). Indicateurs des gains environnementaux, cycle77 % Décrire le contexte économique, social, réglementaire. dans lequel se situe 78 % le projet en présentant une analyse des enjeux sociaux, économiques, environnementaux, 79 % industriels. Donner si possible des arguments chiffrés, par exemple, pertinence et 80 % portée du projet par rapport à la demande économique (analyse du marché, analyse des 81 % tendances), analyse de la concurrence, indicateurs de réduction de coûts, perspectives 82 % de marchés (champs d'application, .). Indicateurs des gains environnementaux, cycle 83 83 % de vie. 84 84 \end{verbatim} … … 111 111 various application domains. The ``high end'' lines concern only FPGA with high logic capacity able 112 112 to implement complex systems. 113 This market is in significant expansion and is estimated to 914 \,M\$ in 2012.113 This market is in significant expansion and is estimated to 914 M\$ in 2012. 114 114 Using FPGA limits the NRE costs to design cost. This boosts the developpment of methodologies 115 115 and tools to automize design and reduce its cost. … … 140 140 segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC 141 141 emulation and prototyping, Mil/aero etc. HPC market size is estimated today by FPGA providers 142 to 214 \,M\$.142 to 214 M\$. 143 143 This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion 144 144 of FPGA-based solutions is limited by the flow automation. Nowadays, there are neither commercial … … 149 149 a synthesized netlist, simulation test bench and custom software library that reflect the hardware 150 150 configuration. 151 Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors\emph{I 152 (Steven) disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this} and to 151 Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to 153 152 simulate the platform at a high design level (system C). 154 153 In addition, SOPC Builder is proprietary and only works together with Altera's Quartus compilation … … 164 163 However, this tool targets only DSP based algorithms. 165 164 \\ 166 Consequently, designer sdevelopping an embedded system needs to master for example165 Consequently, designer developping an embedded system needs to master for example 167 166 SoCLib for design exploration, 168 167 SOPC Builde at the platform level, … … 170 169 and Quartus for design implementation. 171 170 This requires an important tools interfacing effort and makes the design process very complex 172 and achievable only by designers skilled in manydomains.171 and achievable only by designers skilled in various domains. 173 172 COACH project integrates all these tools in the same framework masking them to the user. 174 173 The objective is to allow \textbf{pure software} developpers to realize embedded systems. … … 189 188 % 1.2. POSITIONNEMENT DU PROJET 190 189 % (2 pages maximum) 191 % Pr ï¿œciser :192 % - positionnement du projet par rapport au contexte d ï¿œveloppï¿œ prï¿œcï¿œdemment :193 % vis- ï¿œ-vis des projets et recherches concurrents, complï¿œmentaires ou antï¿œrieurs,190 % Préciser : 191 % - positionnement du projet par rapport au contexte développé précédemment : 192 % vis- à-vis des projets et recherches concurrents, complémentaires ou antérieurs, 194 193 % des brevets et standards. 195 % - positionnement du projet par rapport aux axes th ï¿œmatiques de l'appel ï¿œprojets.196 % - positionnement du projet aux niveaux europ ï¿œen et international.194 % - positionnement du projet par rapport aux axes thématiques de l'appel à projets. 195 % - positionnement du projet aux niveaux européen et international. 197 196 \end{verbatim} 198 197 \end{scriptsize} … … 204 203 \\% IRISA 205 204 The project will also borrow from the ROMA ANR project (2007-2009) and the ongoing 206 joint INRIA-STMicro Nano2012 project. In particular we will adapt existing pattern207 ex traction algorithms and datapath merging techniques to the synthesis of customized205 joint INRIA-STMicro Nano2012 project. In particular we will adapt 206 existing pattern extraction algorithms and datapath merging techniques to the synthesis of customized 208 207 ASIP processors. 209 \\210 \textcolor{gris75}{Steven : Je propose de rajouter un lien avec le projet BioWic~:~on the HPC211 application side, we also hope to benefit from the experience in hardware acceleration of212 bioinformatic algorithms/workfows gathered by the CAIRN group in the context of the ANR213 BioWic project (2009-2011), so as to be able to validate the framework on214 real-life HPC applications.}215 216 208 \par 217 209 %%% 1 -- POUVEZ VOUS CHACUN AJOUTER SVP (SI POSSIBLE) UNE LIGNE 218 210 %%% 1 -- REFERANT UN PROJET ANR OU EUROPEEN 219 %%% 1 -- Projets europ ï¿œens ou ANR rï¿œutilisï¿œs ou continuï¿œs211 %%% 1 -- Projets européens ou ANR réutilisés ou continués 220 212 %%% 1 LIP6/TIMA/LAB-STIC OK 221 213 Regarding the expertise in High Level Synthesis (HLS), the project leverages on know-how acquired over 15 years … … 228 220 Atlantique benefits from several years of expertise in the domain of retargetable compiler (Armor/Calife 229 221 since 1996, and the Gecos compilers since 2002). 230 231 232 222 % LIP FIXME:UN:PEU:LONG ET HORS:SUJET 233 223 %CA% The source-level transformations required by the HLS tools will be … … 300 290 \hspace{2cm}\begin{scriptsize}\begin{verbatim} 301 291 % 2. DESCRIPTION SCIENTIFIQUE ET TECHNIQUE 302 % 2.1. ï¿œTAT DE L'ART292 % 2.1. ÉTAT DE L'ART 303 293 % (3 pages maximum) 304 % D ï¿œcrire le contexte et les enjeux scientifiques dans lequel se situe le projet305 % en pr ï¿œsentant un ï¿œtat de l'art national et international dressant l'ï¿œtat des306 % connaissances sur le sujet. Faire appara ï¿œtre d'ï¿œventuels rï¿œsultats prï¿œliminaires.307 % Inclure les r ï¿œfï¿œrences bibliographiques nï¿œcessaires en annexe 7.1.294 % Décrire le contexte et les enjeux scientifiques dans lequel se situe le projet 295 % en présentant un état de l'art national et international dressant l'état des 296 % connaissances sur le sujet. Faire apparaître d'éventuels résultats préliminaires. 297 % Inclure les références bibliographiques nécessaires en annexe 7.1. 308 298 \end{verbatim} 309 299 \end{scriptsize} … … 408 398 409 399 \subsubsection{Application Specific Instruction Processors} 410 411 ASIP (Application-Specific Instruction-Set Processor) are programmable processors in 412 which both the instruction and the micro architecture have been tailored to a given 413 application domain (eg. video processing), or to a specific application. 414 This specialization usually offers a good compromise between performance (w.r.t a pure software 415 implementation on an embeded CPU) and flexibility (w.r.t an application specific 400 ASIP (Application-Specific Instruction-Set Processor) are programmable 401 processors in which both the instruction and the micro architecture have 402 been tailored to a given application domain (eg. video processing), or 403 in some extreme cases to a specific application (eg H264 specific ASIP). 404 This processor specialization usually offers a good compromise between 405 performance (compared to a pure software implementation on a COTS 406 embeded processor) and flexibility (compared to an application specific 416 407 hardware co-processor). 417 In spite of their obvious advantages, using/designing ASIPs remains a difficult 418 task, since it involves designing both a micro-architecture and a compiler for this 419 architecture. Besides, to our knowledge, there is still no available open-source 420 design flow\footnote{There are commercial tools such a } for ASIP design even if such a tool would 421 be valuable in the context of a System Level design exploration tool. 422 423 In this context, ASIP design based on Instruction Set Extensions (ISEs) has 424 received a lot of interest [NIOSII,TENSILICA]%~\cite{NIOS2,ST70}, 425 as it makes micro architecture synthesis 426 more tractable \footnote{ISEs rely on a template micro-architecture in which 427 only a small fraction of the architecture has to be specialized}, and help ASIP 428 designers to focus on compilers, for which there are still many open problems 429 [CODES04,FPGA08]. 430 This approach however has a strong weakness, since it also significantly reduces 431 opportunities for achieving good seedups (most speedup remain between 1.5x and 432 2.5x), since ISEs performance is generally tied down by I/O constraints as 433 they generally rely on the main CPU register file to access data. 434 435 % ( 436 %automaticcaly extraction ISE candidates for application code \cite{CODES04}, 437 %performing efficient instruction selection and/or storage resource (register) 438 %allocation \cite{FPGA08}). 439 440 441 To cope with this issue, recent approaches~[DAC09,DAC08]%\cite{DAC09,DAC08} 442 advocate the use of 443 micro-architectural ISE models in which the coupling between the processor micro-architecture 444 and the ISE component is thightened up so as to allow the ISE to overcome the register 445 I/O limitations, however these approaches tackle the problem for a compiler/simulation 446 point of view and not address the problem of generating synthesizable representations for 447 these models. 448 449 We therefore strongly believe that there is a need for an open-framework which 450 would allow researchers and system designers to : 451 \begin{itemize} 452 \item Explore the various level of interactions between the original CPU micro-architecure 453 and its extension (for example throught a Domain Specific Language targeted at micro-architecture 454 specification and synthesis). 455 \item Retarget the compiler instruction-selection (or prototype nex passes) passes so as 456 to be able to take advantage of this ISEs. 457 \item Provide a complete System-level Integration for using ASIP as SoC building blocks 458 (integration with application specific blocks, MPSoc, etc.) 459 \end{itemize} 460 461 \hspace{2cm} 462 \begin{scriptsize}\begin{verbatim} 463 464 [CODES08] Theo Kluter, Philip Brisk, Paolo Ienne, and Edoardo Charbon, Speculative DMA for 465 Architecturally Visible Storage in Instruction Set Extensions 466 467 [DAC09] Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon, Way Stealing: Cache-assisted 468 Automatic Instruction Set Extensions. 469 470 [CODES04] Pan Yu, Tulika Mitra, Scalable Custom Instructions Identification for 471 Instruction Set Extensible Processors. 472 473 [FPGA08] Quang Dinh, Deming Chen, Martin D. F. Wong, Efficient ASIP Design for Configurable 474 Processors with Fine-Grained Resource Sharing. 475 476 [NIOSII] Nios II Custom Instruction User Guide 477 478 \end{verbatim} 479 480 \end{scriptsize} 481 %, either 482 %because the target architecture is proprietary, or because the compiler 483 %technology is closed/commercial. 484 485 486 487 488 % We propose to explore how to tighten the coupling of the extensions and 489 % the underlyoing template micro-architecture. 490 % * Thightne Even if such 491 % an approach offers less flexiblity and forbids very tight coupling 492 % between the extensions and the template micro-architecture, it makes the 493 % design of the micro-architecture more tractable and amenable to a fully 494 % automated flow. 495 % \\ 496 % \\ 497 % In the context of the COACH project, we propose to add to the 498 % infra-structure a design flow targeted to automatic instruction set 499 % extension for the MIPS-based CPU, which will come as a complement or an 500 % alternative to the other proposed approaches (hardware accelerator, 501 % multi processors). 502 % 408 \\ 409 As a consequence, this type of architecture is a very attractive choice 410 as a System on chip building block. In spite of their obvious 411 advantages, using/designing ASIPs remains a difficult task, since it 412 involves designing both an efficient micro-architecture and implementing 413 an efficient compiler for this 414 specific micro-architecture. 415 \\ 416 Recently, the use of instruction set extensions has received a lot of 417 interest from the embedded systems design community [NIOS2,FSL,ST70], 418 since it allows to rely on a template micro-architecture in which only a 419 small fraction of the architecture has to be specialized. Even if such 420 an approach offers less flexiblity and forbids very tight coupling 421 between the extensions and the template micro-architecture, it makes the 422 design of the micro-architecture more tractable and amenable to a fully 423 automated flow. 424 \\ 425 However, to our knowledge, there is still no available open-source 426 design flow addressing those two design challenges together, either 427 because the target architecture is proprietary, or because the compiler 428 technology is closed/commercial. 429 \\ 430 In the context of the COACH project, we propose to add to the 431 infra-structure a design flow targeted to automatic instruction set 432 extension for the MIPS-based CPU, which will come as a complement or an 433 alternative to the other proposed approaches (hardware accelerator, 434 multi processors). 503 435 504 436 \subsubsection{Automatic Parallelization} … … 654 586 % 2.2. OBJECTIFS ET CARACTERE AMBITIEUX/NOVATEUR DU PROJET 655 587 % (2 pages maximum) 656 % D ï¿œcrire les objectifs scientifiques/techniques du projet.657 % Pr ï¿œsenter l'avancï¿œe scientifique attendue. Prï¿œciser l'originalitï¿œ et le caractï¿œre588 % Décrire les objectifs scientifiques/techniques du projet. 589 % Présenter l'avancée scientifique attendue. Préciser l'originalité et le caractère 658 590 % ambitieux du projet. 659 % D ï¿œtailler les verrous scientifiques et techniques ï¿œ lever par la rï¿œalisation du projet.660 % D ï¿œcrire ï¿œventuellement le ou les produits finaux dï¿œveloppï¿œs ï¿œl'issue du projet661 % montrant le caract ï¿œre innovant du projet.662 % Pr ï¿œsenter les rï¿œsultats escomptï¿œs en proposant si possible des critï¿œres de rï¿œussite663 % et d' ï¿œvaluation adaptï¿œs au type de projet, permettant d'ï¿œvaluer les rï¿œsultats en591 % Détailler les verrous scientifiques et techniques à lever par la réalisation du projet. 592 % Décrire éventuellement le ou les produits finaux développés à l'issue du projet 593 % montrant le caractère innovant du projet. 594 % Présenter les résultats escomptés en proposant si possible des critères de réussite 595 % et d'évaluation adaptés au type de projet, permettant d'évaluer les résultats en 664 596 % fin de projet. 665 % Le cas ï¿œchï¿œant (programmes exigeant la pluridisciplinaritï¿œ), dï¿œmontrer l'articulation597 % Le cas échéant (programmes exigeant la pluridisciplinarité), démontrer l'articulation 666 598 % entre les disciplines scientifiques. 667 599 \end{verbatim} … … 683 615 \item[SoC design] In this phase, 684 616 The user can obtain simulators at different abstraction levels of the SoC by giving to COACH framework 685 a SoC description. 617 a SoC description. 686 618 This description consists of a process network corresponding to the SoC application, 687 619 an OS, an instance of a generic hardware platform … … 695 627 loading the bitstream on FPGA and running the executable on PC. 696 628 \end{description} 697 629 698 630 % l'avancee scientifique attendue. Preciser l'originalite et le caractere 699 631 % ambitieux du projet. … … 759 691 %% %3.1. PROGRAMME SCIENTIFIQUE ET STRUCTURATION DU PROJET 760 692 %% %(2 pages maximum) 761 %% %Pr ï¿œsentez le programme scientifique et justifiez la dï¿œcomposition en tï¿œches du762 %% %programme de travail en coh ï¿œrence avec les objectifs poursuivis.763 %% %Utilisez un diagramme pour pr ï¿œsenter les liens entre les diffï¿œrentes tï¿œches693 %% %Présentez le programme scientifique et justifiez la décomposition en tâches du 694 %% %programme de travail en cohérence avec les objectifs poursuivis. 695 %% %Utilisez un diagramme pour présenter les liens entre les différentes tâches 764 696 %% %(organigramme technique) 765 %% %Les t ï¿œches reprï¿œsentent les grandes phases du projet. Elles sont en nombre limitï¿œ.766 %% %N'oubliez pas les activit ï¿œs et actions correspondant ï¿œ la dissï¿œmination et ï¿œla697 %% %Les tâches représentent les grandes phases du projet. Elles sont en nombre limité. 698 %% %N'oubliez pas les activités et actions correspondant à la dissémination et à la 767 699 %% %valorisation. 768 700 %% … … 772 704 %% %3.2. MANAGEMENT DU PROJET 773 705 %% %(2 pages maximum) 774 %% %Pr ï¿œciser les aspects organisationnels du projet et les modalitï¿œs de coordination775 %% %(si possible individualisation d'une t ï¿œche coordination : cf. tï¿œche 0 du document706 %% %Préciser les aspects organisationnels du projet et les modalités de coordination 707 %% %(si possible individualisation d'une tâche coordination : cf. tâche 0 du document 776 708 %% %de soumission A). 777 709 %% \subsection{} 778 710 %% %3.3. DESCRIPTION DES TRAVAUX PAR TACHE 779 %% %(id ï¿œalement 1 ou 2 pages par tï¿œche)780 %% %Pour chaque t ï¿œche, dï¿œcrire :781 %% %- les objectifs de la t ï¿œche et ï¿œventuels indicateurs de succï¿œs,782 %% %- le responsable de la t ï¿œche et les partenaires impliquï¿œs (possibilitï¿œde711 %% %(idéalement 1 ou 2 pages par tâche) 712 %% %Pour chaque tâche, décrire : 713 %% %- les objectifs de la tâche et éventuels indicateurs de succès, 714 %% %- le responsable de la tâche et les partenaires impliqués (possibilité de 783 715 %% %l'indiquer sous forme graphique), 784 %% %- le programme d ï¿œtaillï¿œ des travaux par tï¿œche,785 %% %- les livrables de la t ï¿œche,716 %% %- le programme détaillé des travaux par tâche, 717 %% %- les livrables de la tâche, 786 718 %% %- les contributions des partenaires (le " qui fait quoi "), 787 %% %- la description des m ï¿œthodes et des choix techniques et de la maniï¿œre dont788 %% %les solutions seront apport ï¿œes,789 %% %- les risques de la t ï¿œche et les solutions de repli envisagï¿œes.790 791 792 793 794 795 719 %% %- la description des méthodes et des choix techniques et de la manière dont 720 %% %les solutions seront apportées, 721 %% %- les risques de la tâche et les solutions de repli envisagées. 722 723 724 725 726 727
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