Index: /anr/section-1.tex
===================================================================
--- /anr/section-1.tex	(revision 99)
+++ /anr/section-1.tex	(revision 100)
@@ -35,5 +35,5 @@
 The COACH environment will integrate several hardware and software technologies:
 \begin{description}
-\item[Design Space Exploration]
+\item[Design Space Exploration:]
     The COACH environment will support design space exploration to help the
     system designer to select and parameterize the target architecture, and to
@@ -43,5 +43,5 @@
     These criteria will be evaluated by using the SoCLib virtual prototyping infrastructure
     and high-level estimation methodologies.
-\item[Hardware Accelerators Synthesis (HAS)]
+\item[Hardware Accelerators Synthesis (HAS):]
     COACH will allow the automatic generation of hardware accelerators when required.
     Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor
@@ -53,5 +53,5 @@
     The HLS tools of COACH will support a common language and coding style to avoid
     re-engineering by the designer.
-\item[Platform based design] 
+\item[Platform based design:] 
     COACH will handle both \altera and \xilinx FPGA devices.
     COACH will define architectural templates that can be customized by adding
@@ -70,5 +70,5 @@
     Moreover, the specification of the application will be independant of both the
     architectural template and the target FPGA device.
-\item[Hardware/Software communication middleware]
+\item[Hardware/Software communication middleware:]
     Coach will implement an homogeneous HW/SW communication infrastructure and
     communication APIs (Application Programming Interface), that will be used for 
@@ -96,4 +96,6 @@
 The COACH project does not start from scratch.
 It stronly relies on SoCLib virtual prototyping platform~\cite{soclib} for prototyping,
+
+\mustbecompleted{FIXME == SUPPRIMER LE H de Mutek ???}
 (DSX, component library), operating systems (MutekH, DNA/OS).
 It also leverages on  several existing technologies: