Index: /anr/anr.tex =================================================================== --- /anr/anr.tex (revision 120) +++ /anr/anr.tex (revision 121) @@ -47,7 +47,7 @@ \def\Sformat#1{\begin{small}\textsc{#1}\end{small}} \def\inria{INRIA\xspace} \def\Sinria{\Sformat{INRIA}\xspace} -\def\irisa{INRIA/CAIRN\xspace} \def\Sirisa{\Sformat{CAIRN}\xspace} +\def\irisa{INRIA/CAIRN\xspace} \def\Sirisa{\Sformat{IN/CN}\xspace} %\def\citi{CITI\xspace} \def\Sciti{\Sformat{CITI}\xspace} -\def\lip{INRIA/COMPSYS\xspace} \def\Slip{\Sformat{COMP}\xspace} +\def\lip{INRIA/COMPSYS\xspace} \def\Slip{\Sformat{IN/CS}\xspace} \def\tima{TIMA\xspace} \def\Stima{\Sformat{TIMA}\xspace} \def\ubs{LAB-STICC\xspace} \def\Subs{\Sformat{UBS}\xspace} Index: /anr/gantt.l =================================================================== --- /anr/gantt.l (revision 120) +++ /anr/gantt.l (revision 121) @@ -42,6 +42,6 @@ struct partner_def { char *key, *name, *fnfull, *fnshort; } partner_table[] = { { "UNKNOW" ,"relax" ,0 ,0 }, - { "irisa" ,"irisa" ,"table_irisa_full.tex" ,"table_irisa_short.tex" }, - { "lip" ,"lip" ,"table_lip_full.tex" ,"table_lip_short.tex" }, + { "irisa" ,"irisa" ,"table_inria_cairn_full.tex" ,"table_inria_cairn_short.tex" }, + { "inria_compsys" ,"inria_compsys" ,"table_inria_compsys_full.tex" ,"table_inria_compsys_short.tex" }, { "tima" ,"tima" ,"table_tima_full.tex" ,"table_tima_short.tex" }, { "ubs" ,"ubs" ,"table_ubs_full.tex" ,"table_ubs_short.tex" }, @@ -781,4 +781,5 @@ prepare2(curr); prepare3(curr); + do_partner_table_full(1); do_partner_table_short(1); do_partner_table_full(3); do_partner_table_short(3); do_partner_table_full(4); do_partner_table_short(4); Index: /anr/section-6.1.tex =================================================================== --- /anr/section-6.1.tex (revision 120) +++ /anr/section-6.1.tex (revision 121) @@ -1,4 +1,4 @@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsubsection{\inria} +\subsubsection{\inria (CAIRN \& COMPSYS teams)} Inria, the French national institute for research in computer science Index: /anr/section-7.tex =================================================================== --- /anr/section-7.tex (revision 120) +++ /anr/section-7.tex (revision 121) @@ -2,12 +2,42 @@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 1: \inria} -\ressourcehelp - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsubsection*{\irisa} - - -\subsubsection*{\lip} +\subsection{Partner 1: \irisa} + +\begin{figure}\leavevmode\center +\input{table_inria_cairn_full.tex} +\caption{\label{ress-detail-irisa}Man power in $mm$ for the delivrables of \irisa.} +\end{figure} +\begin{description} +\item [Equipment] +No specific equipment acquisition. +\item [Personnel costs] The faculty members involved in the project + are François Charot (INRIA researcher) Steven Derrien (associate + professor) and Charles Wagner (research engineer). The non-permanent + personal required is a PhD student that will mainly work on ASIP + generation. We are looking for profile with strong informatic skills + and good knowledge in computer architecture. + +The table below summarizes the man power by task for both permanent and +non-permanent personnels. The detail by delivrables is given in +figure~\ref{ress-detail-irisa}. +The non-permanent personnels costs represent ??\% of the personnal +costs. The requested funding for non permanent personnels is 100\% of +the total ANR requested funding. + \begin{center}\input{table_inria_cairn_short.tex}\end{center} + +\item [Subcontracting] +No subcontracting costs. +\item [Travel] +The travel costs are associated to project meeting as +well as participation to conferences. The travel costs are estimated +to ??\% of the total requested ANR funding. +\item [Expenses for inward billing] +The costs justified by internal invoicing procedures are evaluated to 4\% +of the total requested ANR funding.\\ +\end{description} + + +\subsection{Partner 2: \lip} + %\ressourcehelp \begin{figure}\leavevmode\center @@ -49,5 +79,5 @@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 2: \tima} +\subsection{Partner 3: \tima} \begin{figure}\leavevmode\center \input{table_tima_full.tex} @@ -90,5 +120,5 @@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 3: \ubs} +\subsection{Partner 4: \ubs} \begin{figure}\leavevmode\center \input{table_ubs_full.tex} @@ -125,5 +155,5 @@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 4: \upmc} +\subsection{Partner 5: \upmc} \begin{figure}\leavevmode\center \input{table_upmc_full.tex} @@ -159,5 +189,5 @@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 5: \xilinx} +\subsection{Partner 6: \xilinx} \begin{figure}\leavevmode\center @@ -184,5 +214,5 @@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 6: \bull} +\subsection{Partner 7: \bull} \begin{description} @@ -205,13 +235,13 @@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 7: \thales} +\subsection{Partner 8: \thales} \ressourcehelp %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 8: \zied} +\subsection{Partner 9: \zied} \ressourcehelp %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 9: \navtel} +\subsection{Partner 10: \navtel} \ressourcehelp Index: /anr/task-2.tex =================================================================== --- /anr/task-2.tex (revision 120) +++ /anr/task-2.tex (revision 121) @@ -85,5 +85,5 @@ the SystemC modules of the components of the ALTERA architectural template currently not available in the SocLib component library. - \itemL{18}{24}{h}{\Sirisa}{ALTERA architecture}{0:0:0} + \itemL{18}{24}{h}{\Sirisa}{ALTERA architecture}{6:6:0} The synthesizable VHDL description of the MWMR component corresponding to the SystemC module of the former delivrable (\csgAlteraSystemC); Index: /anr/task-3.tex =================================================================== --- /anr/task-3.tex (revision 120) +++ /anr/task-3.tex (revision 121) @@ -27,8 +27,8 @@ \itemV{0}{18}{X}{\Sirisa}{ASIP compilation flow} In this first version of the software, the computations patterns corresponding to - custom instruction are specified by the user, and then automatically extracted (when + custom instructions are specified by the user, and then automatically extracted (when beneficial) from the application intermediate representation. %\mustbecompleted{FIXME .....} - \itemL{18}{24}{X}{\Sirisa}{ASIP compilation flow}{0:0:0} + \itemL{18}{24}{X}{\Sirisa}{ASIP compilation flow}{6:9:0} In this second version, the software will also be able to automatically identify interesting pattern candidates in the application code, and use them as custom @@ -37,23 +37,23 @@ \item In this sub-task, we provide micro-architectural template models for the two target - processor architectures (NIOS-II and MIPS) supported within in the COACH-ASIP design flow. + processor architectures (NIOS-II and MIPS) supported within the COACH-ASIP design flow. For each processor, we provide a simulation model (System-C) and a synthesizable model (VHDL) of the architecture, along with its architectural extensions \begin{livrable} \itemV{0}{12}{X}{\Sirisa}{SystemC for extensible MIPS } - { A SystemC simulation model for an simple extensible MIPS architectural template } - \itemL{12}{20}{X}{\Sirisa}{SystemC for extensible MIPS}{0:0:0} - {A SystemC simulation model for a extensible MIPS with a tight architectural integration of + { A SystemC simulation model for a simple extensible MIPS architectural template } + \itemL{12}{20}{X}{\Sirisa}{SystemC for extensible MIPS}{2:3:0} + {A SystemC simulation model for an extensible MIPS with a tight architectural integration of its instruction set extensions} - \itemL{0}{12}{X}{\Sirisa}{SystemC for NIOS processor}{0:0:0} + \itemL{0}{12}{X}{\Sirisa}{SystemC for NIOS processor}{2:0:0} { A SystemC simulation model for an extensible NIOS processor template, the VHDL model being already available from Altera} \itemV{12}{18}{H}{\Sirisa}{VHDL for an extensible MIPS} - {A synthesizable VHDL model for an simple extensible MIPS architectural template} - \itemL{18}{24}{H}{\Sirisa}{VHDL for an extensible MIPS}{0:0:0} - {A synthesizable VHDL model for a extensible MIPS with a tight architectural integration of + {A synthesizable VHDL model for a simple extensible MIPS architectural template} + \itemL{18}{24}{H}{\Sirisa}{VHDL for an extensible MIPS}{9:12:0} + {A synthesizable VHDL model for an extensible MIPS with a tight architectural integration of its instruction set extensions} - \itemL{24}{36}{D}{\Sirisa}{Evaluation report }{0:0:0} - {A evaluation report with quantitative analysis of the performance/area trade-off induced by + \itemL{24}{36}{D}{\Sirisa}{Evaluation report }{0:0:2} + {An evaluation report with quantitative analysis of the performance/area trade-off induced by the different approaches} \end{livrable}