Index: anr/section-4.4.tex
===================================================================
--- anr/section-4.4.tex	(revision 113)
+++ anr/section-4.4.tex	(revision 126)
@@ -47,7 +47,8 @@
     supported.
     The main restriction are:
-    1) The HAS tools have not been yet enhanced, 
+    1) The backend HAS tools have not been yet enhanced, 
     2) dynamic partial reconfiguration is not supported,
-    3) \mustbecompleted{FIXME:ALL .....}
+    3) 
+	4)\mustbecompleted{FIXME:ALL .....}
 \item[Final Release ($T0+36$)]
 \end{description}
@@ -57,29 +58,28 @@
 at the integration phase is significantly reduced.
 \par
-The project has several critical issues:
+The risks that have been identified at the beginning of the project are the following:
 \begin{description}
-\item[\xcoachplus format (\novers{\specXcoachDoc}, \novers{\specXcoachToCA})]
-    Because all the HAS tools rely on it, it is a
-    crucial task. There are no work-arround but as mentionned in
-    section~\ref{xcoach-problem} (page~\pageref{xcoach-problem}) we have worked on it
-	for a year and are confident.
-\item[\xcoachplus format (\novers{\specXcoachDoc},
-      \novers{\specXcoachToSystemC}, \novers{\specXcoachToVhdl})]
-    Its aim is the generation of the coprocessors (hardware \& prototyping model).
-    By centralizing the coprocessor generation, it guarantees their functioning
-    independently of the used HAS tools.
-	Our experience with UGH and GAUT give us confidence in the succes of this
-	task.
-\item[prototyping of ALTERA \& XILINX architectural templates ({\csgAlteraSystemC},
-     {\csgXilinxSystemC}]
-     The SocLib component library contains most of the SystemC models used for the
-     prototyping description of the ALTERA and XILINX architectural templates.
-     Nevertheless, at this time we do not know how many are missing and if the existing
-     are really useables.
-     If the work of theses tasks is too important, they will be abandoned.
-     In this case the work-arround to prototype the XILINX and ALTERA architectural
-     templates is to use the COACH one. These architectures being very similar, the
-     simulation results must be proportional. Theses tasks will be changed by measuring
-     the deviance.
+\item[\xcoach format (\novers{\specXcoachDoc}, \novers{\specXcoachToCA})]
+	Partners have to agree on a convenient exchange format for all tools involved.
+	Because all the HAS tools rely on it, the \xcoach format specification is a
+    crucial step. There are no work-arround but as mentionned in
+    section~\ref{xcoach-problem} (page~\pageref{xcoach-problem}) the five academic partners have worked on it
+	for a full year and a first document already exists.
+%\item[\xcoachplus format (\novers{\specXcoachDoc},
+%      \novers{\specXcoachToSystemC}, \novers{\specXcoachToVhdl})]
+%    Its aim is the generation of the coprocessors (hardware \& prototyping model).
+%    By centralizing the coprocessor generation, it guarantees their functioning
+%    independently of the used HAS tools.
+%	Our experience with UGH and GAUT give us confidence in the succes of this
+%	task.
+\item[Virtual prototyping of ALTERA \& XILINX architectural templates ({\csgAlteraSystemC},
+     {\csgXilinxSystemC})]
+     The SocLib component library contains several SystemC models used for the virtual
+     prototyping of the ALTERA and XILINX architectural templates (NIOS and Microblaze processor cores).
+     Nevertheless, at this time we do not know how many IP cores SystemC simulation models have to be developped.
+     If the workload of this simulation model development is too important, virtual prototyping
+	 of those architectural templates will not be directly supported.
+	 The three architectural templates being quite similar, the virtual
+	 prototyping will use the neutral architectural template.
 \item[VCI/AVALON \& VCI/PLB bridges (\novers{\hpcAvalonBridge}, \novers{\hpcPlbBridge})]
      If one of these tasks is impossible or too important or leads to inefficiency,
@@ -87,5 +87,5 @@
      In this case, the COACH architectural template will not be available for HPC and
      a SystemC VCI model corresponding to the PCI/X IP will be developped to allow
-     prototyping.
+     virtual prototyping.
 \end{description}
 
