Index: /anr/anr.tex =================================================================== --- /anr/anr.tex (revision 125) +++ /anr/anr.tex (revision 126) @@ -103,12 +103,12 @@ Acronym of the proposal & COACH \\\hline Title of the proposal in French & - \textbf{C}onception d'\textbf{A}rchitecture par + \textbf{C}onception d'\textbf{A}rchitecture sur FPGA par \textbf{C}ompilation et synt\textbf{H}\`{e}se\\\hline \begin{minipage}{\linewidth}Title of the proposal in\\ English\end{minipage} - & \mustbecompleted{FIXME} \\\hline -Theme \mustbecompleted{FIXME} & \setlength{\unitlength}{5.0mm}\begin{picture}(20,1) + & ARchitecture DEsign on FPGA by COmpilation and synthesis \\\hline +Theme & \setlength{\unitlength}{5.0mm}\begin{picture}(20,1) \put( 0.5,0){\framebox(0.6,0.6){X}} \put( 1.5,0){1} - \put( 3.5,0){\framebox(0.6,0.6){X}} \put( 4.5,0){2} - \put( 6.5,0){\framebox(0.6,0.6){X}} \put( 7.5,0){3} + \put( 3.5,0){\framebox(0.6,0.6){/}} \put( 4.5,0){2} + \put( 6.5,0){\framebox(0.6,0.6){/}} \put( 7.5,0){3} \put( 9.5,0){\framebox(0.6,0.6){ }} \put(10.5,0){4} \put(12.5,0){\framebox(0.6,0.6){ }} \put(13.5,0){5} Index: /anr/section-4.1.tex =================================================================== --- /anr/section-4.1.tex (revision 125) +++ /anr/section-4.1.tex (revision 126) @@ -69,5 +69,4 @@ simulator. Once the partitioning is validated, the design of the FPGA part is done through \verb!CSG! (figure~\ref{archi-csg}). -\mustbecompleted{FIXME == MODIFICATION DE LA FIGURE} \parlf The project is split into 8 tasks numbered from 1 to 8. There are described Index: /anr/section-4.2.tex =================================================================== --- /anr/section-4.2.tex (revision 125) +++ /anr/section-4.2.tex (revision 126) @@ -1,12 +1,16 @@ \begin{description} \item[Project management structure] -First of all, a good management requires that each task is assigned to a Task Leader. +Each task is assigned to a Task Leader. The Task Leaders assist the project leader in the technical organization, effort -management, of the co-operation and the reporting of the progress. Each month the Task -Leaders have to send to the project leader short update report with the -main high-lights, major opportunities and problems according to the work-plan. +management, of the co-operation and the reporting of the progress. +A steering committee is composed by task leaders and the project leader. +The steering committee has a monthly conference call and is in charge of conflict +management if necessary. +Each task leader has to report on the main high-lights, major +opportunities and problems according to the work-plan. +The redaction of the 6-month reports is the responsability of the steering committee. Therefore, each Partner has the responsibility to monthly inform the task Leaders of the current development of the \ST he has in charge. -COACH will be organized in \mustbecompleted{FIXME: 8} tasks whose interactions are presented in +COACH will be organized in 8 tasks whose interactions are presented in Figure~\ref{dependence-task}. Index: /anr/section-4.4.tex =================================================================== --- /anr/section-4.4.tex (revision 125) +++ /anr/section-4.4.tex (revision 126) @@ -47,7 +47,8 @@ supported. The main restriction are: - 1) The HAS tools have not been yet enhanced, + 1) The backend HAS tools have not been yet enhanced, 2) dynamic partial reconfiguration is not supported, - 3) \mustbecompleted{FIXME:ALL .....} + 3) + 4)\mustbecompleted{FIXME:ALL .....} \item[Final Release ($T0+36$)] \end{description} @@ -57,29 +58,28 @@ at the integration phase is significantly reduced. \par -The project has several critical issues: +The risks that have been identified at the beginning of the project are the following: \begin{description} -\item[\xcoachplus format (\novers{\specXcoachDoc}, \novers{\specXcoachToCA})] - Because all the HAS tools rely on it, it is a - crucial task. There are no work-arround but as mentionned in - section~\ref{xcoach-problem} (page~\pageref{xcoach-problem}) we have worked on it - for a year and are confident. -\item[\xcoachplus format (\novers{\specXcoachDoc}, - \novers{\specXcoachToSystemC}, \novers{\specXcoachToVhdl})] - Its aim is the generation of the coprocessors (hardware \& prototyping model). - By centralizing the coprocessor generation, it guarantees their functioning - independently of the used HAS tools. - Our experience with UGH and GAUT give us confidence in the succes of this - task. -\item[prototyping of ALTERA \& XILINX architectural templates ({\csgAlteraSystemC}, - {\csgXilinxSystemC}] - The SocLib component library contains most of the SystemC models used for the - prototyping description of the ALTERA and XILINX architectural templates. - Nevertheless, at this time we do not know how many are missing and if the existing - are really useables. - If the work of theses tasks is too important, they will be abandoned. - In this case the work-arround to prototype the XILINX and ALTERA architectural - templates is to use the COACH one. These architectures being very similar, the - simulation results must be proportional. Theses tasks will be changed by measuring - the deviance. +\item[\xcoach format (\novers{\specXcoachDoc}, \novers{\specXcoachToCA})] + Partners have to agree on a convenient exchange format for all tools involved. + Because all the HAS tools rely on it, the \xcoach format specification is a + crucial step. There are no work-arround but as mentionned in + section~\ref{xcoach-problem} (page~\pageref{xcoach-problem}) the five academic partners have worked on it + for a full year and a first document already exists. +%\item[\xcoachplus format (\novers{\specXcoachDoc}, +% \novers{\specXcoachToSystemC}, \novers{\specXcoachToVhdl})] +% Its aim is the generation of the coprocessors (hardware \& prototyping model). +% By centralizing the coprocessor generation, it guarantees their functioning +% independently of the used HAS tools. +% Our experience with UGH and GAUT give us confidence in the succes of this +% task. +\item[Virtual prototyping of ALTERA \& XILINX architectural templates ({\csgAlteraSystemC}, + {\csgXilinxSystemC})] + The SocLib component library contains several SystemC models used for the virtual + prototyping of the ALTERA and XILINX architectural templates (NIOS and Microblaze processor cores). + Nevertheless, at this time we do not know how many IP cores SystemC simulation models have to be developped. + If the workload of this simulation model development is too important, virtual prototyping + of those architectural templates will not be directly supported. + The three architectural templates being quite similar, the virtual + prototyping will use the neutral architectural template. \item[VCI/AVALON \& VCI/PLB bridges (\novers{\hpcAvalonBridge}, \novers{\hpcPlbBridge})] If one of these tasks is impossible or too important or leads to inefficiency, @@ -87,5 +87,5 @@ In this case, the COACH architectural template will not be available for HPC and a SystemC VCI model corresponding to the PCI/X IP will be developped to allow - prototyping. + virtual prototyping. \end{description} Index: /anr/section-5.tex =================================================================== --- /anr/section-5.tex (revision 125) +++ /anr/section-5.tex (revision 126) @@ -42,5 +42,5 @@ For commercial use, commercial licenses will be negociated between the owners and the customers. \item -The proprietary ALTERA and XILINX IP core libraries are commercial products +The proprietary ALTERA, XILINX and FLEXRAS IP core libraries are commercial products that are not involved by the free software policy, but these libraries will be supported by the synthesis tools developped in the Coach project. Index: /anr/section-7.tex =================================================================== --- /anr/section-7.tex (revision 125) +++ /anr/section-7.tex (revision 126) @@ -223,5 +223,5 @@ A permanent engineer will be assigned full time to the project for a duration of 20 months as shown in the table below: - \begin{center}\input{table_bull_short.tex}\end{center} + \begin{center}\input{table_bull_full.tex}\end{center} \item[Subcontracting] No subcontracting costs. @@ -242,10 +242,8 @@ for these FPGA boards is estimated to 20 k\euro (6\% of the total ANR funding). \item[Personnel costs] - \mustbecompleted{ The effort to adapt SPEAR DE to generator the input files to COACH framework is - estimated to 22 man.month (6 in task 6 and 16 in task 7). - The effort to describe and develop the application is estimated to 12 man.month. - Finally we need 2 man.month for the partiticipation to the global specification in task 2. - } + estimated to 13 man.months. + The effort to describe and develop the application is estimated to 14 man.month. + Finally we need 1 man.month for the partiticipation to the global specification in task 2. \begin{center}\input{table_thales_full.tex}\end{center} \item[Subcontracting] Index: /anr/task-0.tex =================================================================== --- /anr/task-0.tex (revision 125) +++ /anr/task-0.tex (revision 126) @@ -1,9 +1,9 @@ \begin{taskinfo} \let\UPMC\leader -\let\ALL\disable +\let\ALL\enable \end{taskinfo} % \begin{objectif} -This task relies to the monitoring of the COACH project. Its main objectives are: +This task relates to the monitoring of the COACH project. Its main objectives are: \begin{itemize} \item To ensure the appropriate progress of the project, Index: /anr/task-1.tex =================================================================== --- /anr/task-1.tex (revision 125) +++ /anr/task-1.tex (revision 126) @@ -52,4 +52,5 @@ document listing all the COACH software components and how they cooperate. \begin{livrable} + \CoutHorsD{0}{12}{\Sthales}{user specification}{1:0:0} \itemL{0}{6}{d}{\Supmc}{decription of \ganttlf software architecture}{1:0:0} It contains the software list and the data flow among them. Index: /anr/task-2.tex =================================================================== --- /anr/task-2.tex (revision 125) +++ /anr/task-2.tex (revision 126) @@ -16,8 +16,7 @@ \item the development of all the missing components (SytemC models and/or synthesizable VHDL models of the IP-cores), -\item the configuration and the development of drivers \mustbecompleted{FIXME:: driver de quoi ???} -of the operating systems, -\item the CSG software that generates the SystemC simulators for prototyping and the synthesizable description -of the FPGA-SoC system (i.e. its bitstream), \mustbecompleted{FIXME:: VHDL ou bitstream ???} +\item the configuration and the development of drivers of the operating systems (Board Support Package, HAL), +\item the CSG software that generates the SystemC simulators for prototyping and the FPGA-SoC system +including its bitstream and software executable code, \item the specification of enhanced communication schemes and their sofware and hardware implementations. \end{itemize} @@ -35,19 +34,18 @@ hardware architecture template. \itemV{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly} - This milestone adds to CSG the support to the XILINX and ALTERA architectural - templates and to the enhanced communication system. - In this milestone only the SystemC prototyping will be supported for the XILINX - and ALTERA architectural template. - HAS is available. \mustbecompleted{FIXME:: ca veut dire ???} + The second release of CSG supports the XILINX and ALTERA architectural + templates and the enhanced communication system, but only for SystemC prototyping. + This release integrates a first integration of HLS tools. \itemV{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch} This milestone extends CSG (\csgPrototypingOnly) to FPGA-SoC generation for the XILINX and ALTERA architectural template. \itemL{24}{36}{x}{\Supmc}{CSG}{6:6:6} - Maintenance work of CSG. + Final release of CSG. \end{livrable} \subtask This \ST deals with the components of the architectural templates. \\ - For the COACH architectural template, it consists of the devlopment of the VHDL - synthesizable description of the missing components. \mustbecompleted{FIXME :: pas clair missing components} + For the COACH architectural template, it consists of the development of the VHDL + synthesizable description of the missing communication components (MWMR) + in order to support the process network communication model. Notice that the SystemC models comes from the SocLib ANR project, the processor with its cache comes from the TSAR @@ -55,6 +53,4 @@ \\ For the XILINX and ALTERA architectural templates, we use the XILINX and ALTERA IPs (NIOS, Microblaze, memories, busses...). - The missing component is the MWMR used for communication between the tasks of the - application. \begin{livrable} \itemL{0}{12}{h}{\Supmc}{COACH architecture}{1:0:0} @@ -111,6 +107,5 @@ \begin{livrable} \itemV{6}{8}{x}{\Supmc}{MUTEK OS} - The drivers \mustbecompleted{FIXME :: ???} - required for the first CSG milestone (delivrable \csgCoachArch). + The drivers required for the first CSG milestone (delivrable \csgCoachArch). \itemV{8}{18}{x}{\Supmc}{MUTEK 0S} The drivers required for the second CSG milestone ({\csgPrototypingOnly}). Index: /anr/task-3.tex =================================================================== --- /anr/task-3.tex (revision 125) +++ /anr/task-3.tex (revision 126) @@ -2,4 +2,7 @@ \let\LIP\leader \let\IRISA\enable +\let\UBS\enable +\let\UPMC\enable +\let\TIMA\enable \end{taskinfo} % @@ -15,5 +18,4 @@ as possible, identify communication channels, and output an \xcoach description. -\mustbecompleted {FIXME :: Impossible d'utiliser les transformations de boucles pour amélierer la partie SW ??? } \end{objectif} % Index: /anr/task-4.tex =================================================================== --- /anr/task-4.tex (revision 125) +++ /anr/task-4.tex (revision 126) @@ -95,5 +95,5 @@ \itemL{24}{33}{x}{\Supmc}{frequency calibration}{2:.5:3.5} The frequency calibration software consists of a driver in the FPGA-SoC operating - system and of a control software on a PC. \mustbecompleted {FIXME :: Pas clair pour le HPC. Comprends pas} + system and of a control software. \itemL{24}{27}{d}{\Sxilinx}{optimisation for \ganttlf \xilinx RTL tools (5)}{0:0:1} This deliverable consists in optimizing the VHDL description provided in Index: /anr/task-5.tex =================================================================== --- /anr/task-5.tex (revision 125) +++ /anr/task-5.tex (revision 126) @@ -3,6 +3,8 @@ \begin{taskinfo} -\let\UPMC\leader +\let\BULL\leader +\let\UPMC\enable \let\TIMA\enable +\let\THALES\enable \let\XILINX\enable \end{taskinfo} @@ -14,6 +16,6 @@ \item Providing a software tool that helps the HPC designer to find a good partition of the initial application (figure~\ref{archi-hpc}). -\item Providing communication schemes between the software part running on the PC and the -FPGA-SoC. \mustbecompleted{ FIXME :: Quelle difference avec l'item qui suit ???} +\item specification of the communication schemes between the software part running on the PC and the +FPGA-SoC. \item Implementing the communication scheme at all levels: partition help, software implementation both on the PC and in the operating system of the FPGA-SoC, hardware. @@ -25,5 +27,4 @@ transfers. The reasons of this choices are that both ALTERA and Xilinx provide PCI/X IP for their FPGA and that GPU HPC softwares use also it. -\mustbecompleted { FIXME :: ai supprime (mis en commentaire) la phrse qui suivait} %This will allow us at least to be inspired by GPU communication schemes and may be to reuse %parts of the GPU softwares. @@ -37,5 +38,5 @@ the application part running on the FPGA-SoC. \begin{livrable} - \itemL{0}{6}{d}{\Supmc}{HPC communication API}{1.0:0:0} + \itemL{0}{6}{d}{\Sbull}{HPC communication API}{1.0:0:0} \setMacroInAuxFile{hpcCommApi} Specification describing the API. Index: /anr/task-6.tex =================================================================== --- /anr/task-6.tex (revision 125) +++ /anr/task-6.tex (revision 126) @@ -1,6 +1,6 @@ \begin{taskinfo} -\let\IRISA\leader +\let\IRISA\enable \let\BULL\enable -\let\THALES\enable +\let\THALES\leader \let\NAVTEL\enable \let\ZIED\enable @@ -26,5 +26,5 @@ The deliverable is the specification of the demonstrator in COACH input format defined in the {\specGenManual} deliverable. - \itemL{12}{36}{d}{\Sbull}{\bull demonstrator}{9:6:5} + \itemL{12}{36}{d}{\Sbull}{\bull demonstrator}{9:5:5} Validation of the demonstrator, the deliverable is a document describing the result of the experimentations. @@ -52,5 +52,5 @@ \setMacroInAuxFile{trtAppSpecification} This delivrable is a document that specifies the application. - \itemL{6}{12}{x}{\Sthales}{\thales demonstrator (step 1)}{6:0:0} + \itemL{6}{12}{x}{\Sthales}{\thales demonstrator (step 1)}{4:0:0} This delivrable is the code of the application spcecified former delivrable (\trtAppSpecification). @@ -63,15 +63,7 @@ be able to partition the application on the architecture. \begin{livrable} - \itemL{6}{18}{x}{\Sthales}{SPEAR-DE adaptation}{6:6:0} + \itemL{6}{18}{x}{\Sthales}{SPEAR-DE adaptation}{6:7:0} \setMacroInAuxFile{trtSpearde} Adaptation of SPEAR-DE for COACH framework. - \end{livrable} - - \subtask - abbbaaa - \begin{livrable} - \itemL{6}{18}{x}{\Sthales}{SPEAR-DE adaptation}{6:6:0} - \setMacroInAuxFile{trtSpearde} - bbbb Adaptation of SPEAR-DE for COACH framework. \end{livrable} @@ -90,5 +82,5 @@ (\trtAppSpecification) with SPEAR-DE (\trtSpearde) using COACH milestone of T0+24. The updated code of the application will be also provide. - \itemL{30}{36}{d+x}{\Sthales}{\thales demonstrator (step 2)}{0:6:6} + \itemL{30}{36}{d+x}{\Sthales}{\thales demonstrator (step 2)}{0:5:5} This delivrable is a document that validates and evaluates COACH (final release) for the \thales demonstrators (\trtAppSpecification). Index: /anr/task-7.tex =================================================================== --- /anr/task-7.tex (revision 125) +++ /anr/task-7.tex (revision 126) @@ -1,5 +1,5 @@ \begin{taskinfo} \let\UPMC\leader -\let\XILINX\enable +\let\ALL\enable \end{taskinfo} % @@ -43,7 +43,5 @@ site. The tutorial example will also be used as reference demonstrator of the framework. - The application of this tutorial can be a Motion JPEG application, or an application - that draws in 3D (under open GL) a simulation of a meteor cloud attracted by a sun and - planets, or a database management system. + The application of this tutorial will be a Motion JPEG application. \begin{livrable} \itemV{0}{6}{x}{\Supmc}{tutorial specification}