Index: /anr/task-6.tex
===================================================================
--- /anr/task-6.tex	(revision 128)
+++ /anr/task-6.tex	(revision 129)
@@ -112,17 +112,23 @@
         generate the SoC architecture.
         This delivrable is a document that describes this architecture.
-      \itemL{6}{12}{h}{\Szied}{eFPGA/VCI component}{3.6:0:0}
+      \itemL{6}{18}{h}{\Szied}{eFPGA/VCI component}{3.6:3.6:0}
         FLEXRAS has to adapt the eFPGA interface to connect it to the VCI bus.
         This delivrable is a VHDL description.
-      \itemL{12}{18}{x}{\Szied}{bitstream loader port}{0:3.6:0}
-        Port of the bitstream loader to the MUTEK operating system.
-      \itemL{18}{24}{x}{\Szied}{????????????}{0:2.4:0}
-        \mustbecompleted{FIXME:PAS-CLAIR}
-        FLEXRAS will propose a graph of software tasks. The hardware task to be mapped on
-        the FPGA will be generated using the high level synthesis tool of COACH framework. 
+%      \itemL{12}{18}{x}{\Szied}{bitstream loader port}{0:3.6:0}
+%        Port of the bitstream loader to the MUTEK operating system.
+      \itemL{18}{24}{x}{\Szied}{\zied demonstrators}{0:2.4:0}
+        \zied will propose to test COACH framework and the \zied architecture template
+        throught a basic application.
+        This applicattion will containt 3 communicating tasks under the coach format specified
+        in {\novers{\specGenManual}} delivrable.
+        The first one is a hardware task generated by the HAS tools and transformed into
+        a bit stream by the \zied tools.
+        The second is a bitstream loader that will load the bitstream of the first task on
+        the eFPGA.
+        The third is a software task that communicates with the hw task for testing it.
       \itemL{24}{30}{x}{\Szied}{eFPGA characterisation}{0:0:2.4}
         This delivrable is a file under the format defined by the delivrable
-        \specMacroCell that characterizes the eFPGA. This will allows the COACH HLS tools
-        to run taking into account the eFPGA delays.
+        {\specMacroCell} that characterizes the eFPGA. This will allow the COACH HLS tools
+        to take into account the eFPGA delays.
       \itemL{30}{36}{d}{\Szied}{\zied evaluation}{0:0:3.6}
         This delivrable is a document that describes the tests, the validation and the