Index: anr/task-2.tex
===================================================================
--- anr/task-2.tex	(revision 126)
+++ anr/task-2.tex	(revision 134)
@@ -24,20 +24,20 @@
 to allow the demonstrators to start working.
 This release will include the standard communication schemes (base on SocLib MWMR component)
-and support the COACH architectural template for prototyping and hardware generation.
+and support the neutral architectural template for prototyping and hardware generation.
 \end{objectif}
 %
 \begin{workpackage}
-\subtask This \ST corresponds to the Coach System Generator (CSG) software.
+\subtask This \ST corresponds to the COACH System Generator (CSG) software.
     \begin{livrable}
     \itemV{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch}
-        The first software release of the CSG tool that will allow demonstrators to start working by using the COACH
-        hardware architecture template.
+        The first software release of the CSG tool that will allow demonstrators to start
+        working by using the neutral architectural template.
     \itemV{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly}
-        The second release of CSG supports the XILINX and ALTERA architectural
+        The second release of CSG supports the \xilinx and \altera architectural
         templates and the enhanced communication system, but only for SystemC prototyping.
         This release integrates a first integration of HLS tools.
     \itemV{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch}
         This milestone extends CSG (\csgPrototypingOnly) to
-        FPGA-SoC generation for the XILINX and ALTERA architectural template.
+        FPGA-SoC generation for the \xilinx and \altera architectural template.
     \itemL{24}{36}{x}{\Supmc}{CSG}{6:6:6}
         Final release of CSG.
@@ -45,5 +45,5 @@
 \subtask This \ST deals with the components of the architectural templates.
     \\
-    For the COACH architectural template, it consists of the development of the VHDL
+    For the neutral architectural template, it consists of the development of the VHDL
     synthesizable description of the missing communication components (MWMR)
 	in order to support the process network communication model. 
@@ -52,21 +52,21 @@
     ANR project.
     \\
-    For the XILINX and ALTERA architectural templates, we use the XILINX and ALTERA IPs (NIOS, Microblaze, memories, busses...).
+    For the \xilinx and \altera architectural templates, we use the \xilinx and \altera IPs (NIOS, Microblaze, memories, busses...).
     \begin{livrable}
-    \itemL{0}{12}{h}{\Supmc}{COACH architecture}{1:0:0}
+    \itemL{0}{12}{h}{\Supmc}{neutral architecture}{1:0:0}
         \setMacroInAuxFile{csgCoachArchTempl}
         The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components.
     \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimisation (2)}{0:2:0}
        This deliverable consists in optimizing the VHDL descriptions of the components of
-       the COACH architectural template (deliverable \novers{\csgCoachArchTempl}) to the
+       the neutral architectural template (deliverable \novers{\csgCoachArchTempl}) to the
        \xilinx RTL synthesis tools.
        \upmc will provide the VHDL descriptions, \xilinx will provide back a documentation
        listing that proposes VHDL generation enhancements.
-    \itemV{6}{18}{x}{\Stima}{XILINX architecture}
+    \itemV{6}{18}{x}{\Stima}{\xilinx architecture}
         \setMacroInAuxFile{csgXilinxSystemC}
         The SystemC simulation module of the MWMR component with a PLB bus interface plus
-        the SystemC modules of the components of the XILINX architectural template
+        the SystemC modules of the components of the \xilinx architectural template
         currently not available in the SocLib component library.
-    \itemL{18}{24}{h}{\Stima}{XILINX architecture}{9:9:0}
+    \itemL{18}{24}{h}{\Stima}{\xilinx architecture}{9:9:0}
         The synthesizable VHDL description of the MWMR component corresponding to the
         SystemC module of the former delivrable (\csgXilinxSystemC).
@@ -76,10 +76,10 @@
        \tima will provide MWMR VHDL description, \xilinx will provide back a documentation
        listing that proposes VHDL generation enhancements.
-    \itemV{6}{18}{x}{\Sirisa}{ALTERA architecture}
+    \itemV{6}{18}{x}{\Sirisa}{\altera architecture}
         \setMacroInAuxFile{csgAlteraSystemC}
         The SystemC simulation module of the MWMR component with an AVALON bus interface plus
-        the SystemC modules of the components of the ALTERA architectural template
+        the SystemC modules of the components of the \altera architectural template
         currently not available in the SocLib component library.
-    \itemL{18}{24}{h}{\Sirisa}{ALTERA architecture}{6:6:0}
+    \itemL{18}{24}{h}{\Sirisa}{\altera architecture}{6:6:0}
         The synthesizable VHDL description of the MWMR component corresponding to the
         SystemC module of the former delivrable (\csgAlteraSystemC);
@@ -100,18 +100,18 @@
        listing that proposes VHDL generation enhancements.
     \end{livrable}
-\subtask This \ST consists of the configuration of the SocLib MUTEK and DNA operating
+\subtask This \ST consists of the configuration of the SocLib MUTEKH and DNA operating
     system and the development of drivers for the hardware architectural templates
     and enhanced communication schemes defined in \novers{\specCsgManual} delivrable.
-    For the ALTERA and XILINX architectural templates, the OSs must also be ported on
+    For the \altera and \xilinx architectural templates, the OSs must also be ported on
     the NIOS2 and MICROBLAZE processors.
     \begin{livrable}
-    \itemV{6}{8}{x}{\Supmc}{MUTEK OS}
+    \itemV{6}{8}{x}{\Supmc}{MUTEKH OS}
         The drivers required for the first CSG milestone (delivrable \csgCoachArch).
-    \itemV{8}{18}{x}{\Supmc}{MUTEK 0S}
+    \itemV{8}{18}{x}{\Supmc}{MUTEKH 0S}
         The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
-    \itemL{18}{33}{x}{\Supmc}{MUTEK OS}{1:1:2}
+    \itemL{18}{33}{x}{\Supmc}{MUTEKH OS}{1:1:2}
         Maintenance work.
-    \itemL{6}{18}{x}{\Supmc}{Port of MUTEK OS}{1.0:1:0}
-        Porting of MUTEK OS on the NIOS2 and MICROBLAZE processors.
+    \itemL{6}{18}{x}{\Supmc}{Port of MUTEKH OS}{1.0:1:0}
+        Porting of MUTEKH OS on the NIOS2 and MICROBLAZE processors.
     \itemV{6}{8}{x}{\Stima}{DNA OS}
         The drivers required for the first CSG milestone (delivrable \csgCoachArch).
