Index: /anr/section-1.tex =================================================================== --- /anr/section-1.tex (revision 133) +++ /anr/section-1.tex (revision 134) @@ -71,5 +71,5 @@ architectural template and the target FPGA device. \item[Hardware/Software communication middleware:] - Coach will implement an homogeneous HW/SW communication infrastructure and + COACH will implement an homogeneous HW/SW communication infrastructure and communication APIs (Application Programming Interface), that will be used for communications between software tasks running on embedded processors and @@ -97,6 +97,5 @@ It stronly relies on SoCLib virtual prototyping platform~\cite{soclib} for prototyping, -\mustbecompleted{FIXME == SUPPRIMER LE H de Mutek ???} -(DSX, component library), operating systems (MutekH, DNA/OS). +(DSX, component library), operating systems (MUTEKH, DNA/OS). It also leverages on several existing technologies: on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS, Index: /anr/section-2.1.tex =================================================================== --- /anr/section-2.1.tex (revision 133) +++ /anr/section-2.1.tex (revision 134) @@ -38,5 +38,5 @@ choice for low-to-medium volume applications. Since their introduction in the mid eighties, FPGAs evolved from a simple, -low-capacity gate array to devices (\altera STRATIX III, Xilinx Virtex V) that +low-capacity gate array to devices (\altera STRATIX III, \xilinx Virtex V) that provide a mix of coarse-grained data path units, memory blocks, microprocessor cores, on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement @@ -74,5 +74,5 @@ software library that reflect the hardware configuration. %% Steven disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this. -%% IA: ces lignes ont ete verifiees et corrigée pa altera. De plus C2H est plutot limite. +%% IA: ces lignes ont ete verifiees et corrigée pa \altera. De plus C2H est plutot limite. Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to simulate the platform at a high design level (systemC). @@ -96,6 +96,6 @@ \begin{enumerate} \item a virtual prototyping environment such as SoCLib for system level exploration, - \item an architecture compiler (such as SOPC Builder from \altera, or System generator from Xilinx) - to define the hardware architecture, + \item an architecture compiler (such as SOPC Builder from \altera, or System generator + from \xilinx) to define the hardware architecture, \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for coprocessor synthesis, Index: /anr/section-2.2.tex =================================================================== --- /anr/section-2.2.tex (revision 133) +++ /anr/section-2.2.tex (revision 134) @@ -7,5 +7,5 @@ The COACH project answers to several of the challenges found in different axis of the call for proposals. Keywords of the call are indicated below in italic writing. -Axis 1 "Architectures des systemes embarque" : +Axis 1 "Architectures des syst\`{e}mes embarqu\'{e}s" : COACH will address new embedded systems architectures by allowing the design of Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design constraints and objectives (real-time, low-power). It will permit to design complex SoC based on IP cores ((memory, peripherals, network controllers, communication processors), running Embedded Software, as well as an Operating System with associated middleware and API and using hardware accelerator automatically generated. It will also permit to use efficiently different dynamic system management techniques and re-configuration mechanisms. Index: /anr/section-2.tex =================================================================== --- /anr/section-2.tex (revision 133) +++ /anr/section-2.tex (revision 134) @@ -50,5 +50,5 @@ in a plat-form based design flow supporting virtual prototyping and design space exploration. Most building blocks already exist (resulting from previous projects): the GAUT -or UGH synthesis tools, the MutekH or DNA embedded operating systems, the ASIP technology, +or UGH synthesis tools, the MUTEKH or DNA embedded operating systems, the ASIP technology, the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelisation tool, as well as the SoCLib library of systemC simulation models. They must now be integrated in @@ -88,5 +88,5 @@ %\textbf{High Level Synthesis}: When dedicated hardware coprocessors have been %identified as mandatory, they will be generated by the high level synthesis (HLS) tools. -%The Coach framework will integrate various HLS tools, supporting the micro-architectural space +%The COACH framework will integrate various HLS tools, supporting the micro-architectural space %design exploration. Here again, the exploration criteria are cost, throughput, latency %and power consumption. Index: /anr/section-3.1.tex =================================================================== --- /anr/section-3.1.tex (revision 133) +++ /anr/section-3.1.tex (revision 134) @@ -54,15 +54,15 @@ cover the whole system synthesis process in a full automatic way. Moreover, they are bound to a particular device family and to IPs library. -The most commonly used are provided by Altera and Xilinx to promote their +The most commonly used are provided by \altera and \xilinx to promote their FPGA devices. These two representative tools used to synthesize SoC on FPGA are introduced below. \\ -The Xilinx System Generator for DSP~\cite{system-generateur-for-dsp} is a +The \xilinx System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to Simulink that enables designers to develop high-performance DSP -systems for Xilinx FPGAs. +systems for \xilinx FPGAs. Designers can design and simulate a system using MATLAB and Simulink. The tool will then automatically generate synthesizable Hardware Description -Language (HDL) code mapped to Xilinx pre-optimized algorithms. -However, this tool targets only DSP based algorithms, Xilinx FPGAs and +Language (HDL) code mapped to \xilinx pre-optimized algorithms. +However, this tool targets only DSP based algorithms, \xilinx FPGAs and cannot handle a complete SoC. Thus, it is not really a system synthesis tool. \\ @@ -70,5 +70,5 @@ system, to synthesis it, to programm it into a target FPGA and to upload a software application. -% FIXME(C2H from Altera, marche vite mais ressource monstrueuse) +% FIXME(C2H from \altera, marche vite mais ressource monstrueuse) Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors. System Designer must provide the synthesizable description @@ -77,5 +77,5 @@ accurate level. \\ -In addition, Xilinx System Generator and SOPC Builder are closed world +In addition, \xilinx System Generator and SOPC Builder are closed world since each one imposes their own IPs which are not interchangeable. @@ -98,10 +98,11 @@ Moreover, low power consumption constraint is mandatory for embedded systems. However, it is not yet well handled or not handle at all by the synthesis tools already available. -\item The parallelism is extracted from initial algorithmic specification. To get more parallelism or to reduce -the amount of required memory in the SoC, the user must re-write the algorithmic specification while there is -techniques as polyedric transformations to increase the intrinsic parallelism. -\item While they support limited loop transformations like loop unrolling and loop pipelining, current HLS tools -do not provide support for design space exploration neither through automatic loop transformations nor through -memory mapping. +\item The parallelism is extracted from initial algorithmic specification. +To get more parallelism or to reduce the amount of required memory in the SoC, the user +must re-write the algorithmic specification while there is techniques as polyedric +transformations to increase the intrinsic parallelism. +\item While they support limited loop transformations like loop unrolling and loop +pipelining, current HLS tools do not provide support for design space exploration neither +through automatic loop transformations nor through memory mapping. \item Despite they have the same input language (C/C++), they are sensitive to the style in which the algorithm is written. Consequently, engineering work is required to swap from Index: /anr/section-3.2.tex =================================================================== --- /anr/section-3.2.tex (revision 133) +++ /anr/section-3.2.tex (revision 134) @@ -83,5 +83,5 @@ 3 architectural templates that are synthesizable and that can be prototyped, one design space exploration tool, -2 operating systems (DNA/OS and MUTEK. +2 operating systems (DNA/OS and MUTEKH. \\ The framework fonctionality will be demonstrated with the demonstrators Index: /anr/section-4.1.tex =================================================================== --- /anr/section-4.1.tex (revision 133) +++ /anr/section-4.1.tex (revision 134) @@ -32,17 +32,7 @@ hardware) either as a SystemC simulator to prototype and explore quickly the design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and -launch the Xilinx or Altera RTL synthesis tools.} directly downloadable on the +launch the \xilinx or \altera RTL synthesis tools.} directly downloadable on the FPGA device\footnote{Additional partial bitstreams are generated in case of dynamic partial reconfiguration}. -%To proove CSG that COACH is open and CSG is really configurable, COACH will -%basically support 3 architecture template (the COACH template based on a -%MIPS processors and a VCI token ring, the Altera template based on the NIOS -%and AVALON bus, the Xilinx template based on the MICROBLAZE and PLB bus) -%and 2 operating systems (DNA/OS and MUTEK). Furthermore, thus is enforced -%by the \mustbecompleted{FIXME:zied} contribution that consists in -%implementing an other hardware target. -%\\ -%Finally, it is important to notice that this work is a strong -%enhancement of the SocLib software. \parlf The software architecture for HAS is presented in figure~\ref{archi-hls}. Index: /anr/section-4.4.tex =================================================================== --- /anr/section-4.4.tex (revision 133) +++ /anr/section-4.4.tex (revision 134) @@ -36,11 +36,11 @@ written in the COACH input format. This COACH release allows to prototype and to generate the FPGA-SoC. The main restrictions are: - 1) only the COACH architectural template is supported, + 1) only the neutral architectural template is supported, 2) HAS is not available (but prototyping with virtual coprocessors is available), 3) Enhanced communication schemes are not available. \item[Milestone 3 ($T0+18$)] The second COACH release. At this step most of the COACH features are availables. - The main restriction is that COACH can not yet generate FPGA-SoC for ALTERA and XILINX - architectural templates. + The main restriction is that COACH can not yet generate FPGA-SoC for \altera and + \xilinx architectural templates. The others restriction is that the HAS tools are not yet fully operational. \item[Milestone 4 ($T0+24$)] The pre-release of the COACH project. The full design flow is @@ -73,8 +73,8 @@ % Our experience with UGH and GAUT give us confidence in the succes of this % task. -\item[Virtual prototyping of ALTERA \& XILINX architectural templates ({\csgAlteraSystemC}, +\item[Virtual prototyping of \altera \& \xilinx architectural templates ({\csgAlteraSystemC}, {\csgXilinxSystemC})] The SocLib component library contains several SystemC models used for the virtual - prototyping of the ALTERA and XILINX architectural templates (NIOS and Microblaze processor cores). + prototyping of the \altera and \xilinx architectural templates (NIOS and Microblaze processor cores). Nevertheless, at this time we do not know how many IP cores SystemC simulation models have to be developped. If the workload of this simulation model development is too important, virtual prototyping @@ -85,5 +85,5 @@ If one of these tasks is impossible or too important or leads to inefficiency, it will be abandoned. - In this case, the COACH architectural template will not be available for HPC and + In this case, the neutral architectural template will not be available for HPC and a SystemC VCI model corresponding to the PCI/X IP will be developped to allow virtual prototyping. Index: /anr/section-5.tex =================================================================== --- /anr/section-5.tex (revision 133) +++ /anr/section-5.tex (revision 134) @@ -1,30 +1,30 @@ \subsection{Dissemination} -The Coach project will bring new scientific results in various fields, such as high level synthesis, +The COACH project will bring new scientific results in various fields, such as high level synthesis, hardware/software codesign, virtual prototyping, harware oriented compilation techniques, automatic parallelisation, etc. These results will be presented in the relevant International Conferences, namely DATE, DAC, or ICCAD. -More generally, the Coach infrastructure and the design flow supported by the Coach +More generally, the COACH infrastructure and the design flow supported by the COACH tools and libraries will be promoted by proposing tutorials on FPGA oriented system level synthesis in various worshops and conferences. Following the general policy of the SoCLib platform, the COACH project will be an -open infrastructure, and the Coach tools and libraries will available in the framework +open infrastructure, and the COACH tools and libraries will available in the framework of the SoCLib WEB server. This server will be maintened by the UPMC/LIP6 laboratory. \subsection{Exploitation of results} -The main goal of the Coach project is to help SMEs (Small and Medium Enterprises) +The main goal of the COACH project is to help SMEs (Small and Medium Enterprises) to enter the world of MPSoC technologies. For small companies, the cost is a primary concern. Moreover, these companies have not always in-home expertise in hardware design and VHDL modelling. -As the fabrication costs of an ASIC is generally too high for SMEs, the Coach project focus +As the fabrication costs of an ASIC is generally too high for SMEs, the COACH project focus on FPGA technologies. Regarding the design tools, the cost of advanced ESL (Electronic System Design) -tools is an issue, and the Coach project will follow the same general policy as the SoCLib platform : +tools is an issue, and the COACH project will follow the same general policy as the SoCLib platform : \begin{itemize} \item -All software tools supporting the Coach design flow will be available as free software. -All academic partners contributing to the Coach project agreed to distribute the ESL software +All software tools supporting the COACH design flow will be available as free software. +All academic partners contributing to the COACH project agreed to distribute the ESL software tools under the same GPL license as the SoCLib tools. \item @@ -42,7 +42,7 @@ For commercial use, commercial licenses will be negociated between the owners and the customers. \item -The proprietary ALTERA, XILINX and FLEXRAS IP core libraries are commercial products +The proprietary \altera, \xilinx and \zied IP core libraries are commercial products that are not involved by the free software policy, but these libraries will be supported by the -synthesis tools developped in the Coach project. +synthesis tools developped in the COACH project. \end{itemize} @@ -59,5 +59,5 @@ A global consortium agreement will be defined during the first six monts of the project. -As already stated, the Coach project has been prepared during one year by a monthly meeting +As already stated, the COACH project has been prepared during one year by a monthly meeting involving the five academic partners. The general free software policy described in the previous section has been agreed by academic partners and has been Index: /anr/section-6.1.tex =================================================================== --- /anr/section-6.1.tex (revision 133) +++ /anr/section-6.1.tex (revision 134) @@ -150,7 +150,7 @@ Moreover, the LIP6 developped during the last 10 years the UGH tool for high level synthesis of control-dominated coprocessors. -This tool will be modified to be integrated in the Coach design flow. -\parlf -Even if the preferred dissemination policy for the Coach design flow will be the free software policy, +This tool will be modified to be integrated in the COACH design flow. +\parlf +Even if the preferred dissemination policy for the COACH design flow will be the free software policy, (following the SoCLib model), the SoC department is ready to support start-ups : Six startup companies (including \zied) have been created by former researchers from the SoC department of LIP6 between 1997 and 2002. Index: /anr/section-6.2.tex =================================================================== --- /anr/section-6.2.tex (revision 133) +++ /anr/section-6.2.tex (revision 134) @@ -1,8 +1,8 @@ -The Coach project will be coordinated by professor Alain Greiner from +The COACH project will be coordinated by professor Alain Greiner from Université Pierre et Marie Curie. Alain Greiner is the initiator and the main architect of the SoCLib project. This ANR platform for virtual prototyping of MPSoCs involved 6 industrial companies (including ST Microelectronics and Thales) and ten academic laboratories -(5 of them are involved in the Coach project). +(5 of them are involved in the COACH project). The SoCLib project was managed by Thales, but the technical coordination has been done by Alain Greiner, who has a good experience in coordinating large technical projects Index: /anr/task-2.tex =================================================================== --- /anr/task-2.tex (revision 133) +++ /anr/task-2.tex (revision 134) @@ -24,20 +24,20 @@ to allow the demonstrators to start working. This release will include the standard communication schemes (base on SocLib MWMR component) -and support the COACH architectural template for prototyping and hardware generation. +and support the neutral architectural template for prototyping and hardware generation. \end{objectif} % \begin{workpackage} -\subtask This \ST corresponds to the Coach System Generator (CSG) software. +\subtask This \ST corresponds to the COACH System Generator (CSG) software. \begin{livrable} \itemV{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch} - The first software release of the CSG tool that will allow demonstrators to start working by using the COACH - hardware architecture template. + The first software release of the CSG tool that will allow demonstrators to start + working by using the neutral architectural template. \itemV{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly} - The second release of CSG supports the XILINX and ALTERA architectural + The second release of CSG supports the \xilinx and \altera architectural templates and the enhanced communication system, but only for SystemC prototyping. This release integrates a first integration of HLS tools. \itemV{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch} This milestone extends CSG (\csgPrototypingOnly) to - FPGA-SoC generation for the XILINX and ALTERA architectural template. + FPGA-SoC generation for the \xilinx and \altera architectural template. \itemL{24}{36}{x}{\Supmc}{CSG}{6:6:6} Final release of CSG. @@ -45,5 +45,5 @@ \subtask This \ST deals with the components of the architectural templates. \\ - For the COACH architectural template, it consists of the development of the VHDL + For the neutral architectural template, it consists of the development of the VHDL synthesizable description of the missing communication components (MWMR) in order to support the process network communication model. @@ -52,21 +52,21 @@ ANR project. \\ - For the XILINX and ALTERA architectural templates, we use the XILINX and ALTERA IPs (NIOS, Microblaze, memories, busses...). + For the \xilinx and \altera architectural templates, we use the \xilinx and \altera IPs (NIOS, Microblaze, memories, busses...). \begin{livrable} - \itemL{0}{12}{h}{\Supmc}{COACH architecture}{1:0:0} + \itemL{0}{12}{h}{\Supmc}{neutral architecture}{1:0:0} \setMacroInAuxFile{csgCoachArchTempl} The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components. \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimisation (2)}{0:2:0} This deliverable consists in optimizing the VHDL descriptions of the components of - the COACH architectural template (deliverable \novers{\csgCoachArchTempl}) to the + the neutral architectural template (deliverable \novers{\csgCoachArchTempl}) to the \xilinx RTL synthesis tools. \upmc will provide the VHDL descriptions, \xilinx will provide back a documentation listing that proposes VHDL generation enhancements. - \itemV{6}{18}{x}{\Stima}{XILINX architecture} + \itemV{6}{18}{x}{\Stima}{\xilinx architecture} \setMacroInAuxFile{csgXilinxSystemC} The SystemC simulation module of the MWMR component with a PLB bus interface plus - the SystemC modules of the components of the XILINX architectural template + the SystemC modules of the components of the \xilinx architectural template currently not available in the SocLib component library. - \itemL{18}{24}{h}{\Stima}{XILINX architecture}{9:9:0} + \itemL{18}{24}{h}{\Stima}{\xilinx architecture}{9:9:0} The synthesizable VHDL description of the MWMR component corresponding to the SystemC module of the former delivrable (\csgXilinxSystemC). @@ -76,10 +76,10 @@ \tima will provide MWMR VHDL description, \xilinx will provide back a documentation listing that proposes VHDL generation enhancements. - \itemV{6}{18}{x}{\Sirisa}{ALTERA architecture} + \itemV{6}{18}{x}{\Sirisa}{\altera architecture} \setMacroInAuxFile{csgAlteraSystemC} The SystemC simulation module of the MWMR component with an AVALON bus interface plus - the SystemC modules of the components of the ALTERA architectural template + the SystemC modules of the components of the \altera architectural template currently not available in the SocLib component library. - \itemL{18}{24}{h}{\Sirisa}{ALTERA architecture}{6:6:0} + \itemL{18}{24}{h}{\Sirisa}{\altera architecture}{6:6:0} The synthesizable VHDL description of the MWMR component corresponding to the SystemC module of the former delivrable (\csgAlteraSystemC); @@ -100,18 +100,18 @@ listing that proposes VHDL generation enhancements. \end{livrable} -\subtask This \ST consists of the configuration of the SocLib MUTEK and DNA operating +\subtask This \ST consists of the configuration of the SocLib MUTEKH and DNA operating system and the development of drivers for the hardware architectural templates and enhanced communication schemes defined in \novers{\specCsgManual} delivrable. - For the ALTERA and XILINX architectural templates, the OSs must also be ported on + For the \altera and \xilinx architectural templates, the OSs must also be ported on the NIOS2 and MICROBLAZE processors. \begin{livrable} - \itemV{6}{8}{x}{\Supmc}{MUTEK OS} + \itemV{6}{8}{x}{\Supmc}{MUTEKH OS} The drivers required for the first CSG milestone (delivrable \csgCoachArch). - \itemV{8}{18}{x}{\Supmc}{MUTEK 0S} + \itemV{8}{18}{x}{\Supmc}{MUTEKH 0S} The drivers required for the second CSG milestone ({\csgPrototypingOnly}). - \itemL{18}{33}{x}{\Supmc}{MUTEK OS}{1:1:2} + \itemL{18}{33}{x}{\Supmc}{MUTEKH OS}{1:1:2} Maintenance work. - \itemL{6}{18}{x}{\Supmc}{Port of MUTEK OS}{1.0:1:0} - Porting of MUTEK OS on the NIOS2 and MICROBLAZE processors. + \itemL{6}{18}{x}{\Supmc}{Port of MUTEKH OS}{1.0:1:0} + Porting of MUTEKH OS on the NIOS2 and MICROBLAZE processors. \itemV{6}{8}{x}{\Stima}{DNA OS} The drivers required for the first CSG milestone (delivrable \csgCoachArch). Index: /anr/task-3.tex =================================================================== --- /anr/task-3.tex (revision 133) +++ /anr/task-3.tex (revision 134) @@ -49,5 +49,5 @@ \itemL{0}{12}{X}{\Sirisa}{SystemC for NIOS processor}{2:0:0} { A SystemC simulation model for an extensible NIOS processor template, the VHDL model being - already available from Altera} + already available from \altera} \itemV{12}{18}{H}{\Sirisa}{VHDL for an extensible MIPS} {A synthesizable VHDL model for a simple extensible MIPS architectural template} Index: /anr/task-5.tex =================================================================== --- /anr/task-5.tex (revision 133) +++ /anr/task-5.tex (revision 134) @@ -25,5 +25,5 @@ The low level hardware transmission support will be the PCI/X bus which allows high bit-rate -transfers. The reasons of this choices are that both ALTERA and Xilinx provide PCI/X IP for +transfers. The reasons of this choices are that both \altera and \xilinx provide PCI/X IP for their FPGA and that GPU HPC softwares use also it. %This will allow us at least to be inspired by GPU communication schemes and may be to reuse @@ -58,5 +58,5 @@ The PC part of the HPC communication API that comminicates with the FPGA-SOC, a library and probably a LINUX module. - \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEK OS}{0:3:0} + \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEKH OS}{0:3:0} \setMacroInAuxFile{hpcMutekDriver} The FPGA-SoC part of the communication API, a driver. @@ -64,8 +64,8 @@ Port of the {\hpcMutekDriver} driver on the DNA OS. \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1} - Maintenance work of HPC API for both Linux PC and MUTEK OS. + Maintenance work of HPC API for both Linux PC and MUTEKH OS. \end{livrable} \subtask This \ST deals with the implementation of hardware and SystemC modules - required by the COACH architectural template for using the PCI/X IP of \altera and \xilinx. + required by the neutral architectural template for using the PCI/X IP of \altera and \xilinx. \begin{livrable} \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0} @@ -94,6 +94,6 @@ The drivers required by the DNA OS in order to manage dynamic partial reconfiguration inside the SoC-FPGA. - \itemL{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEK drivers}{0:0:1} - Port of the {\hpcDynconfDriver} drivers on the MUTEK OS. + \itemL{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEKH drivers}{0:0:1} + Port of the {\hpcDynconfDriver} drivers on the MUTEKH OS. \itemL{24}{36}{x}{\Stima}{Profiler for \ganttlf dynamic reconfiguration}{0:0:6} Extension of the HPC partionning helper in order to integrate dynamic partial Index: /anr/task-6.tex =================================================================== --- /anr/task-6.tex (revision 133) +++ /anr/task-6.tex (revision 134) @@ -116,9 +116,9 @@ This delivrable is a VHDL description. % \itemL{12}{18}{x}{\Szied}{bitstream loader port}{0:3.6:0} -% Port of the bitstream loader to the MUTEK operating system. +% Port of the bitstream loader to the MUTEKH operating system. \itemL{18}{24}{x}{\Szied}{\zied demonstrators}{0:2.4:0} \zied will propose to test COACH framework and the \zied architecture template throught a basic application. - This applicattion will containt 3 communicating tasks under the coach format specified + This applicattion will containt 3 communicating tasks under the COACH format specified in {\novers{\specGenManual}} delivrable. The first one is a hardware task generated by the HAS tools and transformed into