Index: anr/section-1.tex
===================================================================
--- anr/section-1.tex	(revision 134)
+++ anr/section-1.tex	(revision 165)
@@ -5,4 +5,5 @@
 complex Multi-Processors System on Chip (MPSoC).
 \\
+\mustbecompleted{FIXME :: A relire, j'ai modifie le paragraphe suivant en motivant plus}
 During the last decade, the design of ASICs (Application Specific
 Integrated Circuits) appeared to be more and more reserved to high volume markets, because
@@ -12,8 +13,14 @@
 Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays
 implement a complete MPSoC with multiple processors and several dedicated
-coprocessors for a few keuros per device.
-In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
+coprocessors for a few Keuros per device. Many applications are initially captured 
+algorithmically in High-Level Languages HLLs such as C/C++. This has led to growing interest 
+in tools that can provide an implementation path directly from HLLs to hardware. 
+Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
 Co-design, High-Level Synthesis...) are now mature and allow the automation of
-a system level design flow that targets FPGA devices.
+a system-level design flow. Unfortunately, ESL tool development to date has primarily focused 
+on the design of hard-wired devices i.e. ASICs and ASSPs (Application Specific Standard Product). 
+However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design 
+methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting 
+designs written in C/C++ language and implementing the function straight into FPGA. 
 We believe that coupling FPGA technologies and ESL methodologies
 will allow both SMEs (Small and Medium Enterprise) and
@@ -28,5 +35,5 @@
 They can be embedded (autonomous) applications
 such as personal digital assistants (PDA), ambiant computing components,
-or wireless sensor networks (WSN)
+or wireless sensor networks (WSN).
 They can also be extension boards connected to a PC to accelerate a specific computation,
 as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
@@ -57,25 +64,25 @@
     COACH will define architectural templates that can be customized by adding
     dedicated coprocessors and ASIPs and by fixing template parameters such as
-    the number of embedded processors or the number of sizes of embedde memory banks,
+    the number of embedded processors, the number of sizes of embedded memory banks
     or the embedded the operating system.
+    However, the specification of the application will be independant of both the
+    architectural template and the target FPGA device.
     Basically, the 3 following architectural templates will be provided:
     \begin{enumerate}
-    \item A Neutral architectural template based on the SoCLib IP core library and the
+    \item A \mustbecompleted{FIXME :: Neutral est tres pejoratif. Technology inependent, independant, standard ???} Neutral architectural template based on the SoCLib IP core library and the
       VCI/OCP communication infrastructure.
-    \item An \altera architectural template based on the \altera IP core library and the
-      AVALON system bus.
-    \item A \xilinx architectural template based on the Xlinx IP core library and the PLB
-      system bus.
+    \item An \altera architectural template based on the \altera IP core library, the
+      AVALON system bus and the NIOS processor.
+    \item A \xilinx architectural template based on the Xilinx IP core library, the PLB
+      system bus and the Microblaze processor.
     \end{enumerate}
-    Moreover, the specification of the application will be independant of both the
-    architectural template and the target FPGA device.
 \item[Hardware/Software communication middleware:]
     COACH will implement an homogeneous HW/SW communication infrastructure and
     communication APIs (Application Programming Interface), that will be used for 
     communications between software tasks running on embedded processors and 
-    dedicated hardware coprocessors,
+    dedicated hardware coprocessors.
 \end{description}
 The COACH design flow will be dedicated to system designers, and will as
-much as possible hide the hardware characteristics to the end user.
+much as possible hide the hardware characteristics to the end-user.
 %From the end user point of view, the specification of the application will be
 %independant from both the architectural template and from the selected FPGA
@@ -95,5 +102,5 @@
 \\
 The COACH project does not start from scratch.
-It stronly relies on SoCLib virtual prototyping platform~\cite{soclib} for prototyping,
+It stronly relies on the SoCLib virtual prototyping platform~\cite{soclib} for prototyping,
 
 (DSX, component library), operating systems (MUTEKH, DNA/OS).
@@ -103,5 +110,5 @@
 on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and transformations
 and on the \xilinx and \altera IP core libraries.
-Finally it will use the \xilinx and \altera RTL tools to generate the FPGA configuration
+Finally it will use the \xilinx and \altera logic and phisical synthesis tools to generate the FPGA configuration
 bitstreams.
 \parlf
@@ -112,5 +119,5 @@
 Most of the general software architecture of the proposed design flow (including the
 exchange format specification) has been define by this working group.
-Because the SocLib platform is the base of this project, it may be described as an
+Because the SoCLib platform is the \mustbecompleted{FIXME Fundation, root, basis ???} base of this project, it may be described as an
 extension of the SoCLib platform.
 %The main development steps of the COACH project are: 
@@ -137,7 +144,9 @@
 as a contractual partner providing documentation and manpower; \altera will contribute as a supporter,
 providing documentation and development boards. These two companies are strongly motivated
-to help the COACH project to generate efficient bitsream for both FPGA families.
+to help the COACH project to generate efficient bitsreams for both FPGA families.
 The role of the industrial partners \bull, \thales, \navtel and \zied is to provide
-real use cases to benchmark the COACH design environment.
+real use cases to benchmark the COACH design environment and to analyze the designer productivity 
+imrovments. \mustbecompleted{FIXME :: j'ai ajoute and to analyze OK ?...} \mustbecompleted{FIXME :: FlexRAS
+sont fournisseur de techno et non de uses cases no ???}
 \parlf
 Following the general policy of the SoCLib platform, the COACH project will be an open
