Index: /anr/section-2.tex
===================================================================
--- /anr/section-2.tex	(revision 171)
+++ /anr/section-2.tex	(revision 172)
@@ -10,5 +10,5 @@
 \begin{center}\begin{minipage}{.8\linewidth}\textit{
 The major objective of COACH is to provide to SMEs an open-source framework to design
-embedded systems on FPGA devices.
+embedded systems on FPGA devices by system designers.
 }\end{minipage}\end{center}
 %Current design methodologies provide quite low-level abstraction capabilities, and 
@@ -28,6 +28,6 @@
 During this project, the COACH partners will develop three different architectural templates:
 \begin{enumerate}
-\item An \altera architectural template based on the \altera IP core library and the AVALON system bus.
-\item A \xilinx architectural template based on the \xilinx IP core library and the PLB system bus.
+\item An \altera architectural template based on the \altera IP core library, the AVALON system bus and the NIOS processor.
+\item A \xilinx architectural template based on the \xilinx IP core library, the PLB system bus and the Microblaze processor.
 \item A Neutral architectural template based on the SoCLib IP core library and the VCI/OCP
       communication infrastructure.
@@ -35,5 +35,5 @@
 The proposed design flow starts from a high level description of the application, specified as a set of 
 parallel tasks written in C, without any assumption on the hardware or software implementation
-of these tasks. It let the system
+of these tasks. It lets the system
 designer in charge of expressing the coarse grain parallelism of the application, gives the designer
 the possibility to explore various mapping of the application on the selected template architecture,