Changeset 177
- Timestamp:
- Feb 15, 2010, 3:08:04 PM (15 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
anr/section-2.2.tex
r135 r177 2 2 % Relevance of the proposal 3 3 4 \mustbecompleted {FIXME == AJOUTER LES POINTS QUI SUIVENT sur les 3 axes ???}5 6 --------------------------------------------------------------------------7 The COACH project answers to several of the challenges found in different axis of the call for proposals. Keywords of the call are indicated below in italic writing.8 9 Axis 1 "Architectures des syst\`{e}mes embarqu\'{e}s" :10 11 COACH will address new embedded systems architectures by allowing the design of Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design constraints and objectives (real-time, low-power). It will permit to design complex SoC based on IP cores ((memory, peripherals, network controllers, communication processors), running Embedded Software, as well as an Operating System with associated middleware and API and using hardware accelerator automatically generated. It will also permit to use efficiently different dynamic system management techniques and re-configuration mechanisms.12 13 Axis 2 "Infrastructures pour l'Internet, le calcul intensif ou les services" :14 15 COACH will address High-Performance Computing (HPC) by helping designer to accelerate an application running on a PC by migrating critical parts into a SoC implemented on an FPGA plugged to the PC bus (through a communication link like PCI/X). COACH will reduce the designer effort through the development of tools that translate high level language programs to FPGA configurations. Moreover, Dynamic Partial Reconfiguration will be used for improving HPC performance as well as reducing the required area.16 17 Axis 3 "Robotique et controle/commande" :18 --------------------------------------------------------------------------19 4 20 5 … … 32 17 environment, including communication middleware and tools to support 33 18 developers in the production of embedded software, through all phases of the software lifecycle, 34 from requirements analysis untildeployment and maintenance.19 from requirements analysis downto deployment and maintenance. 35 20 More specifically, COACH focuses on: 36 21 \begin{itemize} … … 53 38 %%% 54 39 \parlf 55 The COACH project will benefit from a number of previous projects:40 The COACH project will benefit from a number of previous recent projects: 56 41 \begin{description} 57 42 \item[SOCLIB] 58 43 The SoCLib ANR platform (2007-2009) is an open infrastructure developped by 10 academic laboratories 59 and 6 industrial companies. 44 (TIMA, LIP6, Lab-STICC, IRISA, ENST, Gipsa-Lab, CEA-LIST, CEA-LETI, CITI, INRIA-Futurs, LIS) and 6 45 industrial companies (Thales Communications, Thomson R\&D, STMicroelectronics, Silicomp, MDS, TurboConcept). 60 46 It supports system level virtual prototyping of shared memory, multi-processors 61 47 architectures, and provides tools to map multi-tasks software application on these … … 125 111 \end{itemize} 126 112 %%% 113 114 115 The COACH project answers to several of the challenges found in different axis of the 116 call for proposals. Keywords of the call are indicated below in italic writing. 117 118 Axis 1 "Architectures des syst\`{e}mes embarqu\'{e}s" : 119 120 COACH will address new embedded systems architectures by allowing the design of 121 Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design 122 constraints and objectives (real-time, low-power). It will permit to design complex SoC 123 based on IP cores (memory, peripherals, network controllers, communication processors), 124 running Embedded Software, as well as an Operating System with associated middleware and 125 API and using hardware accelerator automatically generated. It will also permit to use 126 efficiently different dynamic system management techniques and re-configuration mechanisms. 127 128 Axis 2 "Infrastructures pour l'Internet, le calcul intensif ou les services" : 129 130 COACH will address High-Performance Computing (HPC) by helping designer to accelerate an 131 application running on a PC by migrating critical parts into a SoC implemented on an FPGA 132 plugged to the PC bus (through a communication link like PCI/X). COACH will reduce the designer 133 effort through the development of tools that translate high level language programs to FPGA 134 configurations. Moreover, Dynamic Partial Reconfiguration will be used for improving HPC performance 135 as well as reducing the required area. 136 137 Axis 3 "Robotique et controle/commande" : 138 139 COACH will permit to design complex digital systems based on high-performance multi-core systems. 140 Like in the consumer electronics domain (telecommunication, multimedia), future control applications 141 will employ more and more SoC not just for typical consumer functionality, but also for safety and 142 security applications (by performing complex analyses on data gathered with intelligent sensors, 143 by initiating appropriate responses to dangerous phenomena...). Application domains for such systems 144 are for example the automotive domain, as well as the aerospace and avionics domains (i.e. sophisticated on-board 145 radar systems, collision-detection, intelligent navigation...). 146 Manufacturing technology will also increasingly need high-end vision analysis and high-speed 147 robot control. In all cases, high performance and real time requirements are combined with 148 requirements to low power, low temperature, high dependability, and low cost. 149 150 Axis 5 "S\'{e}curit\'{e} et suret\'{e}" : 151 152 The results of the COACH project will help users to build cryptographic secure systems implemented in 153 hardware or both in software/ hardware in an effective way, substantially enhancing the 154 process productivity of the cryptographic algorithms hardware synthesis, improving the 155 quality and reducing the design time and the cost of synthesised cryptographic devices. 156 157 COACH technologies can be used in both large and small business, as they will permit users to design 158 embedded systems which meet a wide range of requirements: from low cost and low power consuming 159 devices to very high speed devices, based on parallel computing. For enterprises that will use embedded 160 systems designed via the approaches and tools targeted by COACH, there is the potential for greater 161 efficiency, improved business processes and models. The net results: lower costs, faster response times, 162 better service, and higher revenue. 163 164 127 165 \parlf 128 Finally, it is worth to note that this project cover priorities defined by the commission166 Finally, it is worth to note that this project covers priorities defined by the commission 129 167 experts in the field of Information Technolgies Society (IST) for Embedded 130 168 Systems: $<<$Concepts, methods and tools for designing systems dealing with systems complexity
Note: See TracChangeset
for help on using the changeset viewer.