Index: /anr/task-1.tex
===================================================================
--- /anr/task-1.tex	(revision 186)
+++ /anr/task-1.tex	(revision 187)
@@ -45,5 +45,5 @@
         communication schemes defined in the {\specCsgManual} deliverable must be described for
         coprocessor synthesis.
-    \itemL{6}{12}{d}{\Subs}{HAS specification}{1:0:0} \setMacroInAuxFile{specHasManual}
+    \itemL{6}{12}{d}{\Subs}{HAS specification}{1:2:3} \setMacroInAuxFile{specHasManual}
         The final version of the {\specGenManualI} deliverable updated with the first 
 	    feed-backs of the demonstrator \STs.
@@ -119,7 +119,7 @@
         Specification of the GCC driver tool.
     \itemL{3}{9}{x}{\Subs}{GCC/xcoach driver generator}{0:0:0}
-        First elease of the GCC driver tool.
+        First release of the GCC driver tool.
 	%en T0+18 car va peut etre evoluer en fonction du DSE µ-archi
-    \itemL{9}{18}{x}{\Subs}{GCC/xcoach driver generator}{0:0:0}
+    \itemL{9}{12}{x}{\Subs}{GCC/xcoach driver generator}{0:0:0}
         Final release of the GCC driver tool.
     \end{livrable}
Index: /anr/task-2.tex
===================================================================
--- /anr/task-2.tex	(revision 186)
+++ /anr/task-2.tex	(revision 187)
@@ -10,18 +10,18 @@
 This task deals with the prototyping and the generation of FPGA-SoC digital systems.
 Its is described on figure~\ref{archi-csg}.
-Its objective is to allow the system designer to explore the system space design by
-quickly prototyping and then to generate automatically the FPGA-SoC system.
+Its objective is to allow the system designer to explore the design space by
+quickly prototyping and then to automatically generate the FPGA-SoC system.
 This task consists of
 \begin{itemize}
-\item the development of all the missing components (SytemC models and/or synthesizable VHDL models 
+\item The development of all the missing components (SytemC models and/or synthesizable VHDL models 
 of the IP-cores),
-\item the configuration and the development of drivers of the operating systems (Board Support Package, HAL),
-\item the CSG software that generates the SystemC simulators for prototyping and the FPGA-SoC system
+\item The configuration and the development of drivers of the operating systems (Board Support Package, HAL),
+\item The CSG software that generates the SystemC simulators for prototyping and the FPGA-SoC system
 including its bitstream and software executable code,
-\item the specification of enhanced communication schemes and their sofware and hardware implementations.
+\item The specification of enhanced communication schemes and their sofware and hardware implementations.
 \end{itemize}
-This task being based on the SocLib platform, a first release will be delivered at $T0+12$
+This task being based on the SoCLib platform, a first release will be delivered at $T0+12$
 to allow the demonstrators to start working.
-This release will include the standard communication schemes (base on SocLib MWMR component)
+This release will include the standard communication schemes (base on SoCLib MWMR component)
 and support the neutral architectural template for prototyping and hardware generation.
 \end{objectif}
@@ -111,5 +111,5 @@
         The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
     \itemL{18}{33}{x}{\Supmc}{MUTEKH OS}{1:1:2}
-        Maintenance work.
+        Final release of the MUTEKH OS drivers.
     \itemL{6}{18}{x}{\Supmc}{Port of MUTEKH OS}{1.0:1:0}
         Porting of MUTEKH OS on the NIOS2 and MICROBLAZE processors.
@@ -119,5 +119,5 @@
         The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
     \itemL{18}{33}{x}{\Stima}{DNA OS}{6:3:2}
-        Maintenance work.
+        Final release of the DNA OS drivers.
     \itemL{6}{18}{x}{\Stima}{Port of DNA OS}{3:1:0}
         Porting of DNA OS on the NIOS2 and MICROBLAZE processors.