Changeset 189

Timestamp:

Feb 15, 2010, 5:17:58 PM (14 years ago)

Author:

coach

Message:

UBS

File:

• anr/task-7.tex (modified) (2 diffs)

anr/task-7.tex

@@ -49 +49 @@
     \itemV{6}{12}{d+x}{\Supmc}{tutorial}
         The application is split into two communicating parts, the PC part and FPGA-SoC part.
-        Using the features the T0+12 milestone provides,
+        By using the features the T0+12 milestone provides,
         the tutorial describes how this efficient partionning was obtained.
         The FPGA-SoC part is described as communicating task graph. The tutorial also describes
         how a promising task graph can be obtained.
     \itemV{18}{24}{d}{\Supmc}{tutorial}
-%    \mustbecompleted{FIXME: LIP6 :: Avons (UBS) change le lead du livrable OK ?} 
-%    \mustbecompleted{FIXME: LIP6 :: C'est pas possible, car il faut changer aussi
-%    au-dessus c'est le meme livrable en 3 fois. De plus la c'est plus une DOC CSG que HAS.}
         This tutorial shows how a task can be migrated to coprocessor using HAS tools and
         how FPGA-SoC can be generated and run to FPGA. This for HAS tools and and
@@ -62 +59 @@
     \itemL{30}{36}{d}{\Supmc}{tutorial}{2:1:1}
         The final release of the tutorial.
+    \itemV{18}{24}{d}{\Stima}{tutorial}
+        This tutorial shows to generate a complete HW/SW system by using CSG tool.
+    \itemV{18}{24}{d}{\Slip}{tutorial}
+        This tutorial shows to apply loop transformations to a task.
+    \itemV{18}{24}{d}{\Sirisa}{tutorial}
+        This tutorial shows to customize a processor to obtain an ASIP.
+    \itemV{18}{24}{d}{\Subs}{tutorial}
+        This tutorial shows how a task can be synthesized by using HLS tools developped in 
+                the COACH project. 
     \itemL{30}{33}{d}{\Sxilinx}{optimisation for \ganttlf \xilinx RTL tools (6)}{0:0:0.5}
         \xilinx will check that developped tutorial works well with \xilinx tools,