Index: /anr/section-2.1.tex =================================================================== --- /anr/section-2.1.tex (revision 18) +++ /anr/section-2.1.tex (revision 18) @@ -0,0 +1,101 @@ +Microelectronic allows to integrate complicated functions into products, to increase their +commercial attractivity and to improve their competitivity. Multimedia and communication +sectors have taken advantage from microelectronics facilities thanks to developpment of +design methodologies and tools for real time embedded systems. Many other sectors could +benefit from microelectronics if these methologies and tools are adapted to their features. +The Non Recurring Engineering (NRE) costs involded in designing and manufacturing an ASIC is +very high. It costs several milliars of euros for IC factory and several millions to fabricate +a specific circuit for example a conservative estimate for a 65nm ASIC project is 10 million USD. +Consequently, it is generally unfeasible to design and fabricate ASICs in +low volumes and ICs are designed to cover a broad applications spectrum at the cost of +performance degradation. +\\ +Today, FPGAs become important actors in the computational domain that was originally dominated +by microprocessors and ASICs. Just like microprocessors FPGA based systems can be reprogrammed +on a per-application basis. At the same time, FPGAs offer significant performance benefits over +microprocessors implementation for a number of applications. Although these benefits are still +generally an order of magnitude less than equivalent ASIC implementations, low costs +(500 euros to 10K euros), fast time to market and flexibility of FPGAs make them an attractive +choice for low-to-medium volume applications. +Since their introduction in the mid eighties, FPGAs evolved from a simple, +low-capacity gate array technology to devices (Altera STRATIX III, Xilinx Virtex V) that +provide a mix of coarse-grained data path units, memory blocks, microprocessor cores, +on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement +complex systems like multi-processors platform with application dedicated coprocessors. +Table~\ref{fpga_market} shows the estimation of FPGA worldwide market in the next years covering +various application domains. The ``high end'' lines concern only FPGA with high logic capacity able +to implement complex systems. +This market is in significant expansion and is estimated to 914\,M\$ in 2012. +Using FPGA limits the NRE costs to design cost. This boosts the developpment of methodologies +and tools to automize design and reduce its cost. +\begin{table}\leavevmode\center +\begin{tabular}{|l|l|l|l|}\hline +Segment & 2010 & 2011 & 2012 \\\hline\hline +Communications & 1,867 & 1,946 & 2,096 \\ +High end & 467 & 511 & 550 \\\hline +Consumer & 550 & 592 & 672 \\ +High end & 53 & 62 & 75 \\\hline +Automotive & 243 & 286 & 358 \\ +High end & - & - & - \\\hline +Industrial & 1,102 & 1,228 & 1,406 \\ +High end & 177 & 188 & 207 \\\hline +Military/Aereo & 566 & 636 & 717 \\ +High end & 56 & 65 & 82 \\\hline\hline +Total FPGA/PLD & 4,659 & 5,015 & 5,583 \\ +Total High-End FPGA & 753 & 826 & 914 \\\hline +\end{tabular} +\caption{\label{fpga_market} Gartner estimation of worldwide FPGA/PLD consumption (Millions \$)} +\end{table} +\par +Today, several companies (atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp, +Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand +for very high performance (HPC) primes over other requirements. They tend to use the highest +performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative +architectures and algorithms. Companies show up in different "traditional" applications and market +segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC +emulation and prototyping, Mil/aero etc. HPC market size is estimated today by FPGA providers +to 214\,M\$. +This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion +of FPGA-based solutions is limited by the flow automation. Nowadays, there are neither commercial +nor free tools covering the whole design process. +For instance, with SOPC Builder from Altera, users can select and parameterize IP components +from an extensive drop-down list of communication, digital signal processor (DSP), microprocessor +and bus interface cores, as well as incorporate their own IP. Designers can then generate +a synthesized netlist, simulation test bench and custom software library that reflect the hardware +configuration. +Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors\emph{I +(Steven) disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this} and to +simulate the platform at a high design level (system C). +In addition, SOPC Builder is proprietary and only works together with Altera's Quartus compilation +tool to implement designs on Altera devices (Stratix, Arria, Cyclone). +PICO [CITATION] and CATAPULT [CITATION] allow to synthesize coprocessors from a C++ description. +Nevertheless, they can only deal with data dominated applications and they do not handle the +platform level. +The Xilinx System Generator for DSP [http://www.xilinx.com/tools/sysgen.htm] is a plug-in to +Simulink that enables designers to develop high-performance DSP systems for Xilinx FPGAs. +Designers can design and simulate a system using MATLAB and Simulink. The tool will then +automatically generate synthesizable Hardware Description Language (HDL) code mapped to Xilinx +pre-optimized algorithms. +However, this tool targets only DSP based algorithms. +\\ +Consequently, designers developping an embedded system needs to master for example +SoCLib for design exploration, +SOPC Builde at the platform level, +PICO for synthesizing the data dominated coprocessors +and Quartus for design implementation. +This requires an important tools interfacing effort and makes the design process very complex +and achievable only by designers skilled in many domains. +COACH project integrates all these tools in the same framework masking them to the user. +The objective is to allow \textbf{pure software} developpers to realize embedded systems. +\par +The combination of the framework dedicated to software developpers and FPGA target, allows to gain +market share over Multi-core CPUs and GPUs HPC based solutions. +Moreover, one can expect that small and even very small companies will be able to propose embedded +system and accelerating solutions for standard software applications with acceptable prices, thanks + to the elimination of huge hardware investment in opposite to ASIC based solution. +\\ +This new market may explose like it was done by micro-computing in eighties. This success were due +to the low cost of first micro-computers (compared to main frame) and the advent of high level +programming languages that allow a high number of programmers to launch start-ups in software +engineering. +