Changeset 195
- Timestamp:
- Feb 16, 2010, 8:04:07 AM (15 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
anr/section-4.4.tex
r179 r195 36 36 written in the COACH input format. This COACH release allows to prototype and to generate the FPGA-SoC. 37 37 The main restrictions are: 38 1) only the neutral architectural template is supported,38 1) Only the neutral architectural template is supported, 39 39 2) HAS is not available (but prototyping with virtual coprocessors is available), 40 40 3) Enhanced communication schemes are not available. … … 49 49 The main restriction are: 50 50 1) The backend HAS tools have not been yet enhanced, 51 2) dynamic partial reconfiguration is not supported,51 2) Dynamic partial reconfiguration is not supported, 52 52 3) NIOS processor instruction set extension is supported, but only for user specified patterns. 53 53 4)\mustbecompleted{FIXME:ALL .....} … … 55 55 56 56 \end{description} 57 This organisation allows t o advance globally the projectstep by step mixing development57 This organisation allows the project to globally progress step by step mixing development 58 58 and demonstrator deliverables. 59 59 Hence, demonstrator feed-back will arrive early and so the risk to point out incompatibility … … 77 77 \item[Virtual prototyping of \altera \& \xilinx architectural templates ({\csgAlteraSystemC}, 78 78 {\csgXilinxSystemC})] 79 The So cLib component library contains several SystemC models used for the virtual79 The SoCLib component library contains several SystemC models used for the virtual 80 80 prototyping of the \altera and \xilinx architectural templates (NIOS and Microblaze processor cores). 81 81 Nevertheless, at this time we do not know how many IP cores SystemC simulation models have to be developped.
Note: See TracChangeset
for help on using the changeset viewer.