Index: /anr/section-4.4.tex
===================================================================
--- /anr/section-4.4.tex	(revision 194)
+++ /anr/section-4.4.tex	(revision 195)
@@ -36,5 +36,5 @@
     written in the COACH input format. This COACH release allows to prototype and to generate the FPGA-SoC.
     The main restrictions are:
-    1) only the neutral architectural template is supported,
+    1) Only the neutral architectural template is supported,
     2) HAS is not available (but prototyping with virtual coprocessors is available),
     3) Enhanced communication schemes are not available.
@@ -49,5 +49,5 @@
     The main restriction are:
     1) The backend HAS tools have not been yet enhanced, 
-    2) dynamic partial reconfiguration is not supported,
+    2) Dynamic partial reconfiguration is not supported,
     3) NIOS processor instruction set extension is supported, but only for user specified patterns. 
 	4)\mustbecompleted{FIXME:ALL .....}
@@ -55,5 +55,5 @@
 	
 \end{description}
-This organisation allows to advance globally the project step by step mixing development
+This organisation allows the project to globally progress step by step mixing development
 and demonstrator deliverables.
 Hence, demonstrator feed-back will arrive early and so the risk to point out incompatibility
@@ -77,5 +77,5 @@
 \item[Virtual prototyping of \altera \& \xilinx architectural templates ({\csgAlteraSystemC},
      {\csgXilinxSystemC})]
-     The SocLib component library contains several SystemC models used for the virtual
+     The SoCLib component library contains several SystemC models used for the virtual
      prototyping of the \altera and \xilinx architectural templates (NIOS and Microblaze processor cores).
      Nevertheless, at this time we do not know how many IP cores SystemC simulation models have to be developped.