Changeset 198 for anr

Timestamp:

Feb 16, 2010, 8:59:52 AM (15 years ago)

Author:

coach

Message:

minor modifs in 3.1.4

File:

• anr/section-3.1.tex (modified) (3 diffs)

anr/section-3.1.tex

@@ -137 +137 @@
 designers to focus on compilers, for which there are still many open
 problems\cite{ARC08}.
-This approach however has a strong weakness, since it also significantly reduces 
-opportunities for achieving good speedups (most speedup remain between 1.5x and 
+This approach however has a severe weakness, since it also significantly reduces 
+opportunities for achieving good speedups (most speedups remain between 1.5x and 
 2.5x), since ISEs performance is generally tied down by I/O constraints as 
 they generally rely on the main CPU register file to access data.
@@ -148 +148 @@
 To cope with this issue, recent approaches~\cite{DAC09,CODES08,TVLSI06} advocate the use of 
 micro-architectural ISE models in which the coupling between the processor micro-architecture
-and the ISE component is thightened up so as to allow the ISE to overcome the register 
-I/O limitations, however these approaches generally tackle the problem for a compiler/simulation 
-point of view and not address the problem of generating synthesizable representations for 
+and the ISE component is tightened up so as to allow the ISE to overcome the register 
+I/O limitations. However these approaches generally tackle the problem from a compiler/simulation 
+point of view and do not address the problem of generating synthesizable representations for 
 these models. 
 
@@ -159 +159 @@
 and its extension (for example through a Domain Specific Language targeted at micro-architecture
 specification and synthesis).
-\item Retarget the compiler instruction-selection (or prototype nex passes) passes so as
-to be able to take advantage of this ISEs.
+\item Retarget the compiler instruction-selection pass
+(or prototype new passes) so as to be able to take advantage of this ISEs.
 \item Provide  a complete System-level Integration for using ASIP as SoC building blocks 
 (integration with application specific blocks, MPSoc, etc.)