Index: r/.project =================================================================== --- /anr/.project (revision 386) +++ (revision ) @@ -1,22 +1,0 @@ - - - anr - - - - - - net.sourceforge.texlipse.builder.TexlipseBuilder - - - - - fr.irisa.triskell.kermeta.kpm.kpmBuilder - - - - - - net.sourceforge.texlipse.builder.TexlipseNature - - Index: r/.texlipse =================================================================== --- /anr/.texlipse (revision 386) +++ (revision ) @@ -1,13 +1,0 @@ -#TeXlipse project settings -#Wed Nov 25 18:13:04 CET 2009 -builderNum=2 -outputDir= -makeIndSty= -bibrefDir= -outputFormat=pdf -tempDir= -mainTexFile=anr.tex -outputFile=anr.pdf -langSpell= -markDer=true -srcDir= Index: r/Makefile =================================================================== --- /anr/Makefile (revision 386) +++ (revision ) @@ -1,59 +1,0 @@ -# set here all the sources files -# required to build anr.pdf -SOURCES= anr.tex anr.bib anr.sty section-1.tex \ - section-2.tex section-issues.tex section-position.tex \ - flow2.pdf section-etat-de-art.tex section-objectif.tex \ - section-project-description.tex section-project-management.tex \ - architecture-csg.pdf architecture-hls.pdf architecture-hpc.pdf \ - dependence-task-h.pdf \ - task-management.tex task-backbone.tex \ - task-csg.tex task-frontend.tex \ - task-backend.tex task-hpc.tex \ - task-demonstrator.tex task-dissemination.tex \ - section-project-task-schedule.tex \ - section-dissemination.tex \ - section-consortium-desc.tex \ - section-consortium-leader.tex \ - section-consortium-people.tex \ - section-ressources.tex \ - annexe-cv.tex \ - annexe-autre-participation.tex \ - annexe-reponse.tex - -TABLES= \ - table_inria_cairn_full.tex table_inria_cairn_short.tex \ - table_inria_compsys_full.tex table_inria_compsys_short.tex \ - table_tima_full.tex table_tima_short.tex \ - table_ubs_full.tex table_ubs_short.tex \ - table_upmc_full.tex table_upmc_short.tex \ - table_bull_full.tex table_bull_short.tex \ - table_thales_full.tex table_thales_short.tex \ - table_mds_full.tex table_mds_short.tex - -# PROGRAMS -FIG2DEV = fig2dev - -%.pdf: %.fig - @echo "Converting $< to $@" - @$(FIG2DEV) -L pdf -p aaa $< $@ - -anr.pdf: $(SOURCES) gantt - mkdir -p tmp - touch gantt.tex gantt1.tex gantt2.tex $(TABLES) - @echo "Generating pdf file" - @pdflatex anr.tex || true - @bibtex anr - @rm -f table_*.tex - @./gantt < anr.gantt - @pdflatex anr.tex - @pdflatex anr.tex - @grep ndefine anr.log - - -gantt: gantt.l - @flex gantt.l && gcc -g lex.yy.c -o gantt - @rm lex.yy.c - -clean: - rm -f anr.aux anr.bbl anr.blg anr.log anr.out anr.toc anr.pdf - rm -f $(TABLES) gantt.tex gantt1.tex gantt2.tex anr.gantt Index: r/README =================================================================== --- /anr/README (revision 386) +++ (revision ) @@ -1,20 +1,0 @@ -Pour generer le document: - $ make -ou + sur - $ rm anr.pdf ; make - -Pour enlever les annotations anr ou les mustbecompleted - il suffit de commenter les macro dans la section CONFIG - de anr.tex - -Les anciens fichiers sont dans obsoletes. - - -******** GENERATION AUTOMATIQUE DES TABLES BUDGETAIRES******** -Pour remplir automatiquement les tables budgetaires short et full, -il faut renseigner soit le champ itemL s'il s'agit d'un délivrable - \itemL{mois_debut_livrable}{mois_fin}{rien}{\Smonentité}{Description courte du livrable}{cout 1année:2A:3A} - par ex: \itemL{6}{36}{}{\Supmc}{release handling}{1:.5:.5} -soit rajouter un champ cout hors délivrable - \CoutHorsD{mois_debut_livrable}{mois_fin}{\Smonentité}{Description courte du cout}{cout 1année:2A:3A} - par ex: \CoutHorsD{6}{36}{\Stima}{dissemination}{0:2:2} Index: r/annexe-autre-participation.tex =================================================================== --- /anr/annexe-autre-participation.tex (revision 386) +++ (revision ) @@ -1,120 +1,0 @@ -\anrdoc{Un tableau par partenaire (Cf. 5.3)\\ -Mentionner ici les projets en cours de réalisation soit au sein de programmes de -de l'ANR, soit auprÚs d'organismes, de fondations, à l'Union Européenne, etc -que ce soit comme coordinateur ou comme partenaire. Pour chacun, donner le nom de -l'appel à projets, le titre du projet et le nom du coordinateur.} - -\newenvironment{autreprojettabular}{% - \noindent\begin{tabular}{|c|p{1.6cm}|c|p{5.0cm}|p{5.0cm}|p{4.6cm}|p{2.0cm}|}\hline - Part. & Name & - \raisebox{-2.8ex}{{\begin{minipage}[c]{0.8cm}\centering PM\\by\\year\\\end{minipage}}} - & Project name, financing institution, grant allocated - & Project title - & Coordi\-nator name - & Start \& end date - \\\hline\hline - }{\end{tabular}\vspace{.75ex}\\} - -\def\autreprojettabularentry#1#2#3#4#5#6#7{#1 & #2 & #3 & #4 & #5 & #6 & #7 \\\hline} - -%\begin{landscape} -%\begin{figure} -\begin{small} -% -\begin{autreprojettabular} -\autreprojettabularentry - {1}{Avot}{6} - {BDREAMS, MEDEA+, 306 k\euro} - {Design Refinement of Embedded Analogue and Mixed Signal Systems} - {\makebox{Serge Scotti} (STM)} - {01/06/2008 31//05/2012} -\autreprojettabularentry - {1}{Lucas}{6} - {SoCKeT, Systems@tic, 320 k\euro} - {SoC toolKit for critical Embedded sysTems} - {\makebox{Vincent LEFFTZ} (Astrium)} - {01/06/2008 01/12/2011} -%\autreprojettabularentry -% {2}{Greiner}{4} -% {Tsar, CATRENE, 400 k\euro} -% {Tera Scale ARchitecture} -% {\makebox{Huy-Nam} Nguyen (Bull)} -% {04/01/2008 05/31/2011} -%\autreprojettabularentry -% {7}{Nguyen}{8} -% {Tsar, CATRENE, 695 k\euro} -% {Tera Scale ARchitecture} -% {\makebox{Huy-Nam} Nguyen (Bull)} -% {04/01/2008 05/31/2011} -\autreprojettabularentry - {3}{Coussy}{3} - {SoCKeT, System@tic, 177 k\euro} - {SoC toolKit for critical Embedded sysTems} - {\makebox{Vincent LEFFTZ} (Astrium)} - {01/06/2008 01/12/2011} -\autreprojettabularentry - {5}{P\'etrot}{3} - {3DIM3, CATRENE, 741 k\euro} - {3D TSV Integration for MultiMedia and Mobile Applications} - {\makebox{Dominique} Marron (STMicroelectronics)} - {01/02/2009 31/01/2012} -%\autreprojettabularentry -% {5}{P\'etrot}{3} -% {SoftSoC, MEDEA+, 500 k\euro} -% {Software for SoC} -% {\makebox{Anne-Marie} Foulliard (Thales Communications)} -% {1/03/2008 28/02/2011} -\autreprojettabularentry - {5}{P\'etrot}{3} - {ComCas, CATRENE, 600 k\euro} - {Communication-centric heterogeneous Multi-Core Architectures} - {\makebox{Armand} Castillejo (ST-Ericsson)} - {01/03/2009 28/02/2012} -\autreprojettabularentry - {6}{Derrien}{5} - {BioWic, ANR Arpege, 136 k\euro} - {Hardware acceleration of bioinformatic algorithms} - {\makebox{Dominique Lavenier} (IRISA)} - {01/01/2009 31/12/2011} -%\autreprojettabularentry -% {5}{Muller}{4} -% {iGlance, CATRENE, 550 k\euro} -% {Interactive Genius Look At Numerous Contemporary Events} -% {\makebox{Michel} Imbert (STMicroelectronics)} -% {01/07/2008 30/06/2011} -\autreprojettabularentry - {8}{Lemonier}{3} - {FORFOR, ANR Arpege, 305 k\euro} - {Flexible Operating System FOr Reconfigurable platform} - {\makebox{Muller} (LEAT)} - {01/01/2008 31/12/2011} -\autreprojettabularentry - {8}{Lemonier}{4} - {FREIA, ANR Arpege, 280 k\euro} - {FRamework for Embedded Image Applications} - {\makebox{Blondeau} (Amines)} - {01/01/2008 31/12/2011} -\autreprojettabularentry - {8}{Lemonier}{3} - {CHAPI, System@tic, 251 k\euro} - {Solutions pour le Calcul embarqué Hautes performances pour - les APplications Industrielles, petites \& moyennes séries} - {\makebox{Lecluse} (Kalray)} - {01/12/2009 31/12/2012} -\autreprojettabularentry - {8}{Brelet}{4} - {SoCKeT, System@tic, 176 k\euro} - {SoC toolKit for critical Embedded sysTems} - {\makebox{Vincent LEFFTZ} (Astrium)} - {01/01/2010 01/12/2011} -\autreprojettabularentry - {8}{Brelet}{4} - {RTSIMEX ANR, 194 k\euro} - {Retro-ingénierie de Traces d’analyse de SIMulation et d’EXécution de systÚme temps-réel} - {\makebox{Fr\'ed\'eric Thomas} (OBEO)} - {01/01/2010 31/12/2012} -\end{autreprojettabular} -% -\end{small} -%\end{figure} -%\end{landscape} Index: r/annexe-cv.tex =================================================================== --- /anr/annexe-cv.tex (revision 386) +++ (revision ) @@ -1,225 +1,0 @@ -\anrdoc{1 page maximum par personne (Cf. 5.3).} - -\newenvironment{cvenv}[4]{% - % #1 : {Nom}{Prenom}{age} - % #2 : situation actuelle - % #3 : cursus - % #4 : {#}{recent pub} - \noindent - \begin{tabular}{|p{3.3cm}|p{4.3cm}|p{1.4cm}|p{6.3cm}|}\hline - \def\tmp##1##2##3{Name: ##1&First Name: ##2&age: ##3}\tmp#1 - & - \def\tmp##1##2{##1 publications: ##2}\tmp#4 - \\\hline - \end{tabular} - \begin{description} - \item[Situation] #2 - \item[Cursus] #3 - }{\end{description}\vspace*{1.ex}} - -\begin{cvenv} - {{Greiner}{Alain}{58}} - {Professeur UMPC} - {HDR Thesis (1982)} - {{100}{\cite{ag-1} \cite{ag-2} \cite{ag-3} \cite{ag-4}}} - - \item[Projects]\mbox{} - \begin{itemize} - \item Work on TSAR CATRENE project \cite{disydent05}. - \item Worked on SoCLib ANR project\cite{disydent05}. - \item Worked on COSY european project \cite{cosy}. - \end{itemize} -\end{cvenv} -% -\begin{cvenv} - {{Aug\'e}{Ivan}{50}} - {Ma\^itre de conf\'erences at ENSIIE (Evry Essonne)} - {HDR Thesis (2008), Thesis (1990), ENSIIE Engineer (1983)} - {{20}{\cite{ia-hdr} \cite{ugh08} \cite{disydent05}}} - - \item[Courses of lecture] System, Kernel, Network, Computer Architecture, Programing. - \item[Projects]\mbox{} - \begin{itemize} - \item Worked on COSY european project \cite{cosy}. - \item Work on UGH since 1996 \cite{ugh08}. - \item Worked on Disydent \cite{disydent05}. - \end{itemize} - \item[Other work experiences]\mbox{} - \begin{itemize} - \item Work as system administrator since six years at ENSIIE. - \item Worked as a senior engineer for four years at Philips. - \item Worked as engineer for two years at ANIRAL-UTEC. - \end{itemize} -\end{cvenv} -% -\begin{cvenv} - {{Nguyen}{Huy-Nam}{56}} - {Head of MVS Departement at Bull S.A.S} - {Thesis (1982), ENSMP Engineer (1977)} - {{5}{}} - \item[Projects]\mbox{} - \begin{itemize} - \item Coordinator of TSAR CATRENE project \cite{disydent05}. - \item Worked on projects: ITEA/Care4Me, Medea+/NEVA, Medea/MESA, Medea/AT403, Medea/AT407, Jessi/AC3, Jessi/AC8 - \end{itemize} -\end{cvenv} -% -\begin{cvenv} - {{Feautrier}{Paul}{71}} - {Emeritus Professor} - {Th\`ese d'Etat, 1968} - {{100}{\cite{Feau:92aa} \cite{Feau:92bb} \cite{FP:96} \cite{Feau:96} - \cite{syntol}}} - \item[Course of Lectures]\mbox{} - System, System Kernel, Automatic Parallelization, Operation Research, - Compilation (at Universit\'e P. et M. Curie, Universit\'e de Verasilles - and Ecole Normale Sup\'erieure de Lyon). - \item[Projects]\mbox{} - \begin{itemize} - \item ITEA MARTES, 2007--2009. - \end{itemize} - \item[Other Work Experience]\mbox{} - \begin{itemize} - \item PhD thesis in Computational Astrophysics (HPC) 1960--1968. - \end{itemize} -\end{cvenv} -% -\begin{cvenv} - {{Alias}{Christophe}{33}} - {INRIA researcher (CR2)} - {PhD (2005)} - {{11}{\cite{bee}} \cite{ca:nuca} \cite{ca:chuba} \cite{ca:arc}} - \item[Course of Lectures]\mbox{} - Compilers, programming languages, computer architecture, networks. -\end{cvenv} -% -\begin{cvenv} - {{P\'etrot}{Fr\'ed\'eric}{44}} - {Professor } - {PhD (1994), HDR (2003)} - {{75}{\cite{disydent05} \cite{JerrayaPetrot} \cite{mutek} \cite{dna}}} - \item[Course of Lectures]\mbox{} - Computer Architecture, programming language, operating systems, - practical compilation, high-level synthesis. - \item[Projects]\mbox{} - \begin{itemize} - \item Hospi, SoCLib (ANR) - \item Medea AT403, Lomosa - \item OpenTLM, Sceptre (FUI) - \item COSY, Sprint (ESPRIT) - \end{itemize} -\end{cvenv} -% -\begin{cvenv} - {{Muller}{Olivier}{30}} - {Associate Professor} - {PhD (2007)} - {{10}{}} - \item[Course of Lectures]\mbox{} - Computer Architecture, assembly language programming, FPGA - \item[Projects]\mbox{} - \begin{itemize} - \item Medea iGlance - \end{itemize} -\end{cvenv} -% -\begin{cvenv} - {{Charot}{François}{52}} - {INRIA researcher } - {PhD (1982)} - {{50}{\cite{Martin09c} \cite{Martin09d} \cite{Wolinski09a} \cite{RAFFIN:2010:INRIA-00539874:1}}} - \item[Course of Lectures]\mbox{} - embedded system design - \item[Projects]\mbox{} - \begin{itemize} - \item SocLib and ROMA ANR projects -% \item Nano2012 RecMotifs project - \end{itemize} -\end{cvenv} -% -\begin{cvenv} -{{Derrien}{Steven}{36}} -{Associate Professor} -{PhD (2002)} -{{20}{\cite{sd:lomita}} \cite{sd:mmalpha} \cite{sd:hmmer} \cite{sd:rdisk}} -\item[Course of Lectures]\mbox{} -Principles of operating systems, Design of embedded systems, programming languages. -\item[Projects]\mbox{} -\begin{itemize} -\item ANR-Biowic, 2009-- -%\item Nano2012 S2S4HLS, 2009-- -\end{itemize} -\end{cvenv} -% -\begin{cvenv} - {{Coussy}{Philippe}{36}} - {Associate Professor} - {PhD (2003)} - {{47}{ \cite{5605303} \cite{gaut08} \cite{HLSBOOK} \cite{DBLP:journals:dt:CoussyGMT09} - \cite{DBLP:journals:vlsisp:ThabetCHM09}}} - \item[Course of Lectures]\mbox{} - Computer Architecture, programming language, operating systems, - SoC Design, high-level synthesis. - \item[Projects]\mbox{} - \begin{itemize} - \item SoCKeT (FUI) - \item SoCLib (ANR) - \item SystemC'Mantic (RNTL) - \item FLASH (ARC INRIA) - \item ALIPTA (RNRT) - \end{itemize} -\end{cvenv} -% -\begin{cvenv} - {{Chavet}{Cyrille}{32}} - {Associate Professor} - {PhD (2007)} -{{20}{\cite{CHAVET:2007:HAL-00153994:1} \cite{DBLP:conf:iccad:ChavetACCJUM07} -\cite{DBLP:conf:glvlsi:ChavetCUM07} \cite{5605303}}} - \item[Course of Lectures]\mbox{} - Parrallel programming, VHDL, real time programming, database networking - \item[Projects]\mbox{} - \begin{itemize} - \item SoCKeT (FUI) - \end{itemize} -\end{cvenv} -% -\begin{cvenv} - {{Heller}{Dominique}{44}} - {Research Engineer} - {PhD (1998)} - {{24}} - \item[Course of Lectures]\mbox{} - FPGA, VHDL, programming language, HLS - \item[Projects]\mbox{} - \begin{itemize} - \item SoCKeT (FUI) - \item SoCLib (ANR) - \item SystemC'Mantic (RNTL) - \end{itemize} -\end{cvenv} -% -\begin{cvenv} - {{Lemonnier}{Fabrice}{43}} - {Research program manager} - {PhD (1996), Master in parallel computing (1992), EFREI Engineer (1991)} - {{3}{}} - \item[Projects]\mbox{} - \begin{itemize} - \item Coordinator of Teraops project (p\^ole de comp\'etitivit\'e System\verb+@+tic) to develop a heterogeneous manycore - \item Works on FOSFOR and PREIA ANR project on reconfigurable computing, and on CHAPI (p\^ole de comp\'etitivit\'e System\verb+@+tic) - \end{itemize} -\end{cvenv} -% -\begin{cvenv} - {{Brelet}{Paul}{28}} - {software developer} - {EFREI Engineer (2007)} - {{4}{}} - \item[Projects]\mbox{} - \begin{itemize} - \item Worked on toolset in MORPHEUS (ICT FP6) - \item Works on toolset in SOCKET (p\^ole de comp\'etitivit\'e System\verb+@+tic), toolset in RTSimex (ANR) - \end{itemize} -\end{cvenv} - Index: r/annexe-reponse.tex =================================================================== --- /anr/annexe-reponse.tex (revision 386) +++ (revision ) @@ -1,313 +1,0 @@ -%\def\t{\\\hspace*{.5em}} -\def\mysubsection{\subsubsection} -\def\mysubsubsection#1{\subsubsection*{\underline{#1}}} -\def\t{\\{$\bullet$}~} -\def\sectionPpageP#1{section~\ref{#1} (page~\pageref{#1})\xspace} -\def\sectionVpage#1{section~\ref{#1}, page~\pageref{#1}\xspace} -% -Le projet a été soumis en 2010 au programme ARPEGE. -Dans la premiÚre section, nous présentons nos réponses aux suggestions et -remarques des experts en suivant l'ordre du dossier d'évaluation qui nous a été -retourné. La seconde section, quant à elle, synthétise nos réponses par rapport -aux principales faiblesses qui ont été relevée pour la précédente version de la -proposition. -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\mysubsection{Réponses séquentielles} -% -\mysubsubsection{Pertinence de la proposition au regard de l'appel à projet} -Pas de faiblesse signalée. -\mysubsubsection{Qualité scientifique et technique de la proposition} -\begin{description} - \item[Point 1 (\textit{non prise en compte des outils existants})]\mbox{} - \t%\note{O.1} - Pour la synthÚse de bas niveau sur FPGA, nous utiliserons intensivement - les environnements industriels QUARTUS \& ISE. - \t%\note{O.2} - Pour la synthÚse de systÚme, on pourrait effectivement utiliser des outils - tels que SOP C builder, mais ceux-ci ne permettent pas de faire de prototypage - et ne sont pas libres et trop spécifiques à une famille d'IPs propriétaire. - Nous avons donc choisi DSX/SoCLib, car il est open source, et c'est celui que - nous maitrisons le plus et nous savons déjà que son moteur couvre une - grande partie des besoins de COACH à ce niveau. - \t\note{INT} - Enfin COACH ne vise pas les flots de conception de systÚmes complexes tels - que SOCKET, TOPCASED, SPEAR-DE. - COACH se positionne en effet comme une sous-partie de ces flots complets et - doit être considéré comme un point tool. Cependant, dans la nouvelle - version de la proposition, nous avons - \textit{ajouté à COACH ce qui est nécessaire pour qu'il puisse - être intégré dans de tels environnements de conception: - configuration et description des SoC générés en IP-XACT}. - Les livrables {\NOVERStrtSpearde} et {\NOVERSmdsAppSpecification} démontrent cette - possibilité. - \item[Point 2 (\textit{pas de dimension recherche})]\mbox{} - \\ La dimension recherche est présente à différents niveaux de ce projet. - \t%\note{R.1} - Tout d'abord, le fait de synthétiser la même description de haut niveau soit par HLS - soit par ASIP, est à notre connaissance non encore réalisé à ce jour. - \t%\note{R.2} - De plus, l'utilisation de transformations polyédriques dans des outils de HLS - opérationnels n'est pas courant. - \t%\note{R.3} - Les IPs courantes du marché sont des composants matériels certes génériques mais à configuration/paramétrisation limitées. COACH permettra au contraire de concevoir des IPs qui constitueront de véritables sous-systÚmes à fonctionnalités complexes et trÚs paramétrables (hardware + software), il sera - intéressant de voir ce que de tel IP peuvent apporter au monde de la conception de systÚmes embarqués. - \t%\note{R.4} - Les outils de conception de SoC actuels ont soit une approche matérielle - (sans limite sur les choix architecturaux), soit massivement parallÚle à - gros grain (MPSoC à mémoire cohérente). Il en résulte des systÚmes trÚs complexes nécessitant des spécialistes en - matériel (approche matérielle) ou en programmation parallÚle. - A l'opposé, dans COACH l'architecture matérielle est simple et quasiment fixée. - Le moyen d'accélération est le parallélisme à grain trÚs fin généré au sein - des coprocesseurs par HLS. Il en résulte que des développeurs de logiciel - standard pourront utiliser COACH. \\ - La démonstration de la pertinence ou de la non pertinence de ces choix est - à notre avis l'axe de recherche principal du projet car il impactera les orientations - technologiques liées à l'exploitation des plateformes matérielles de demain. - \item[Point 3 (\textit{lien entre HPC et SoC embarqué})]\mbox{} - \\ %\note{X.1} - Le terme HPC est employé dans de nombreux contextes et il est difficile de s'entendre sur sa définition exacte. Dans notre proposition, le terme HPC est - défini section~\ref{HPC:definition} (page~\pageref{HPC:definition}); il - s'agit bien d'une sur-couche du module de conception de SoC - comme illustré sur la figure~\ref{coach-flow} (page~\pageref{coach-flow}).\\ - BriÚvement notre HPC consiste à accélérer une application existante qui - tourne sur un PC. Ceci est fait par: - 1) l'isolation de moteur de calcul de l'application, - 2) l'implantation de ce moteur dans un SoC, - 3) l'ajout d'une carte FPGA sur le bus PCI/E du PC. Le FPGA intÚgrera le SoC.\\ - La façon dont COACH aide l'utilisateur à isoler le moteur de calcul de l'application - est expliquée dans la section~\ref{HPC:howto} (page~\pageref{HPC:howto}) et - sur la figure~\ref{archi-hpc} (page~\pageref{archi-hpc}). - La façon dont l'application accélérée est générée fait l'objet de la - figure~\ref{coach-flow} (page~\pageref{coach-flow}). - \item[Autres]\mbox{} - \begin{description} - \item[État de l'art incomplet]\mbox{} - \\ %\note{EA} - Dans l'état de l'art, nous nous sommes concentrés d'une part sur les outils - de même niveau que COACH, - le HPC (\sectionVpage{soa:hpc}) et - la synthÚse de systÚme (\sectionVpage{soa:system:synthesis}) - et d'autre part sur les technologies utilisées, - la HLS (\sectionVpage{soa:hls}), - l'ASIP (\sectionVpage{soa:asip}), - et la parallélisation automatique - (\sectionVpage{soa:automatic:parallelization}). - \\ %\note{EA} - Nous avions fait l'impasse sur les outils de plus haut niveau de - conception de SoC, ceux-ci n'étant pas directement le sujet de COACH. - Nous avons ajouté le chapitre - \og SoC design flow automation using IP-XACT{\fg} - (\sectionPpageP{soa:ip-xact}) pour palier ce manque. - \\ %\note{EA} - Nous sommes conscients que cet état de l'art est loin d'être complet - mais à notre décharge, il y a le nombre limité de pages et la grande - variété de domaines abordés dans ce projet. - \item[Articulation avec SoCLib]\mbox{}\\ - Voir la note de marge \seenote{SL1} dans la section \ref{coach+soclib} ci-dessous. - \item[Pérennité à long terme du logiciel]\mbox{}\\ - Voir la section \ref{perennite+dissemination} ci-dessous. - \item[Mauvais positionnement du projet]\mbox{}\\ - Concernant la remarque sur un positionnement du projet - en \og plateforme {\fg} plutÃŽt qu'en \og recherche industrielle \fg, - nous avons considéré que l'effort devait être concentré sur les aspects -techniques innovants plutÃŽt que sur leur mise en application dans un nombre important de flots. En -effet, dans la nouvelle mouture, nous utilisons les résultats des projets SoCket et Topcased, avec compatibilité IP-XACT, assurant ainsi une généricité pour l'intégration dans de nombreux flots de production, sans pour autant multiplier à outrance les expérimentations dans le cadre du projet. Ainsi la taille du projet nous permet de rester en positionnement \og recherche industrielle \fg. - \end{description} -\end{description} -% -\mysubsubsection{Qualité de la construction de la proposition} -\begin{description} - \item[Manque un industriel pour assurer la pérennité]\mbox{}\\ - \note{IND1} - Il était mentionné qu'il fallait un industriel pour assurer - la pérennité et la dissémination du projet. \mds est entré dans - le consortium pour assurer ce rÃŽle.\\ - Voyez aussi la section \ref{perennite+dissemination} ci-dessous - pour plus d'information. - \item[Trop ambitieux]\mbox{}\\ - Voir la section \ref{trop:ambitieux} ci-dessous. -\end{description} -% -\mysubsubsection{Impact global du projet} -\begin{description} - \item[Volonté de tout refaire]\mbox{}\\ - \note{REF} - Les experts mentionnent \og une volonté de tout refaire {\fg}. Il est dommage - qu'ils n'aient pas explicité leurs pensées. En effet le projet s'appuie sur - des briques existantes pour la plupart de ses composants et sur les - environnements QUARTUS \& ISE pour la synthÚse de bas niveau.\\ - Les seuls composants manquants sont les composants matériels de - communication mais ils sont incontournables pour la réalisation du projet - sur les trois plateformes cibles. - \item[Trop gros travail de développement]\mbox{}\\ - Voir la section \ref{trop:ambitieux} ci-dessous. - \item[Absence d'utilisation de standard]\mbox{}\\ - \note{STD} - En effet, le projet n'utilisait pas le standard IP-XACT des flots de - conception de SoC. Ceci a été corrigé dans cette soumission en introduisant - le standard IEEE 1685 IP-XACT (livrable \NOVERScsgImplementation), - d'une part en entrée pour faciliter la configuration de COACH sur d'autre plateforme - et d'autre part en ajoutant une sortie au format IP-XACT des SoC générés pour - leur intégration comme sous-systÚme dans les flots de conception de SoC. - Les livrables {\NOVERStrtSpearde} et {\NOVERSmdsAppSpecification} démontrent cette - possibilité. - \item[Utilisation de RTOS non industriels]\mbox{}\\ - L'OS bien qu'indispensable n'est pas une piÚce maitresse du projet. - En effet, on doit pouvoir passer facilement à un autre OS si ce - dernier supporte les thread POSIX. - \item[Le projet est trop basé sur les composants SoCLib]\mbox{}\\ - Voir la note de marge \seenote{SL2} dans la section \ref{coach+soclib} ci-dessous. -\end{description} -% -\mysubsubsection{Qualité du consortium} -\begin{description} - \item[Xilinx n'a pas une part assez active]\mbox{}\\ - Xilinx ne fait plus partie du consortium. - \item[Manque un industriel pour assurer la pérennité]\mbox{}\\ - \note{IND2} - Les experts suggÚrent la société \mds. \mds est entré dans le - consortium pour remplir ce rÃŽle. - \item[Pas de vision pour intégrer COACH dans un flot de conception - industriel]\mbox{}\\ - Voir les notes de marge \seenote{INT} et \seenote{STD} ci-dessus. -\end{description} -% -\mysubsubsection{Moyens humains et financiers} -\begin{description} - \item[Incongruités de quelques demandes financiÚres]\mbox{}\\ - Les experts n'ont pas précisé leurs pensées. Néanmoins, la répartition financiÚre a été complÚtement revue. - - \item[Déséquilibre entre l'ampleur du développement et les moyens]\mbox{}\\ - Voir la section \ref{trop:ambitieux} ci-dessous. - \item[Doute sur la possibilité d'intégrer l'ensemble des outils existants en - un tout cohérent]\mbox{}\\ - \note{DOU} - Un rÃŽle principal de \mds tant que chef de file sera d'assurer la coordination de maniÚre professionnelle de ce projet. - -\end{description} -% -\mysubsubsection{Avis Général} -\begin{description} - \item[Déséquilibre entre l'ampleur du développement et les moyens]\mbox{}\\ - Voir la section \ref{trop:ambitieux} ci-dessous. - \item[Doute sur la possibilité d'intégrer l'ensemble des outils existants en - un tout cohérent]\mbox{}\\ - Voir la note de marge \seenote{DOU} au-dessus. - \item[\parbox{\linewidth}{COACH étant une continuation de SoCLib, - SoCLib n'étant pas une réussite industrielle $\Longrightarrow$ - faut-il financer COACH pour donner une chance à SoCLib?}]\mbox{}\\ - Voir la note de marge \seenote{SL3} dans la section \ref{coach+soclib} ci-dessous. - \item[Manque un industriel pour assurer la pérennité]\mbox{}\\ - Voir les notes de marge \seenote{IND1} et \seenote{IND2} au-dessus. - \item[Justifier le positionnement comme une continuité de SoCLib]\mbox{}\\ - La section \ref{coach+soclib} ci-dessous montre que COACH n'est pas une - continuité de SoCLib et cette justification est donc sans objet. - \item[Absence de considération pour les outils/standard industriels]\mbox{}\\ - Voir les notes de marge \seenote{INT} et \seenote{STD} au-dessus. - \item[Volonté de tout refaire]\mbox{}\\ - Voir la note de marge \seenote{REF} au-dessus. -\end{description} -% -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\mysubsection{SynthÚse} -% -\mysubsubsection{Projet trop ambitieux} -\label{trop:ambitieux} -Par rapport au projet 2010, nous avons réduit la surface du projet de 20\% en nous -concentrant sur le cœur de COACH. Les principales réductions sont: -\begin{itemize} - \item Suppression d'un OS:\\ - Dans la proposition 2010, nous avions choisi 2 OS (Mutekh et DNA) pour - montrer que COACH était indépendant de l'OS. - L'OS bien qu'indispensable n'est pas une piÚce maitresse du projet. - En effet, on doit pouvoir passer facilement à un autre OS si ce - dernier supporte les thread POSIX.\\ - \textit{Nous avons ÃŽté l'OS Mutekh}. Ceci diminue les développements systÚme - de moitié. - \item Suppression de la reconfiguration dynamique:\\ - Dans la proposition 2010, la tâche~6 (PC/FPGA communication middleware) - contenait une partie importante qui consistait à partager le FPGA entre - plusieurs applications et charger dynamiquement certaine de ses parties - en fonction des applications qui tournent sur le PC.\\ - \textit{Nous avons ÃŽté la reconfiguration dynamique}. Ceci diminue de 30 à - 40 \% les développements de la tâche~6 et enlÚve quelques homme mois dans la - tache~3 (System generation). - \item Diminution des développements materiels:\\ - Dans la proposition 2010, nous avions projeté 1) de prototyper les SoC des - différents patrons architecturaux de façon exacte, 2) d'implanter le - composant de communication (MWMR) pour les patrons architecturaux XILINX et ALTERA. - Ces choix conduisaient à 4 implantations du composants de communication - (MWMR) (1 VHDL MWMR/\xilinxbus, 1 VHDL MWMR/AVALON, 1 SystemC - MWMR/\xilinxbus et - 1 SystemC MWMR/AVALON) et probablement à quelques autres modules SystemC.\\ - \textit{Nous avons ÃŽté ces développements}. - En effet pour l'implantation matériel des patrons architecturaux, on - utilisera les ponts VCI/\xilinxbus et VCI/AVALON qui sont nécessaires au HPC et - pour le prototypage, on se limitera au patron architectural neutre. -\end{itemize} -% -\mysubsubsection{Projet \& SoCLib} -\label{coach+soclib} -{$\bullet$}\note{SL1} -Dans l'évaluation de la soumission 2010, les experts se posent plusieurs -questions sur les liens entre le projet COACH et le projet ANR SoCLib. -Pour répondre à ces questions listons les composants de SoCLib utilisés dans COACH: -\begin{itemize} - \item Les descriptions SystemC de 6 composants sur environ 70. - \item L'explorateur de l'espace de conception DSX qui devra être étendu pour - supporter la génération matérielle des architectures (VHDL synthétisable). - \item Un OS sur cinq. -\end{itemize} -Cette liste montre clairement que SoCLib n'est qu'un composant logiciel parmi -la dizaine d'autres sur les quels COACH s'appuie. -Ce n'est pas, et de loin, le plus irremplaçable, les modÚles VHDL du patron -architectural neutre comme les outils de synthÚse seraient bien plus difficiles -à refaire et GCC comme les environnements QUARTUS et ISE sont absolument -indispensables. -\t\note{SL2} -On ne peut donc pas dire que COACH est trop basé sur SoCLIB. -\t\note{SL3} -A la question posée par les experts: - \og faut il financer COACH pour donner une chance à SoCLib? {\fg} -La réponse est que financer COACH n'influencera pas la vie de SoCLib, -les 2 projets n'étant pas assez corrélés. -D'ailleurs COACH pourrait trÚs bien survivre à une mort de SoCLib en maintenant -les quelques composants SoCLib qu'il utilise. -\t\note{SL4} -Enfin une réserve concerne l'utilisation du bus VCI jugé obsolÚte via les composants -SoCLib. Le projet prévoit le développement de pont VCI/AVALON et VCI/\xilinxbus ce qui -permettra l'utilisation des IP de XILINX et ALTERA dans le patron architectural -neutre. -% -\mysubsubsection{Pérennité/dissémination du projet} -\label{perennite+dissemination} -L’arrivée de la société Magillem Design Services dans le consortium permettra de -répondre aux problÚmes liés à la pérennité et la dissémination des résultats du -projets. Le rÃŽle de ce nouveau partenaire sera d’orienter les choix afin de -pouvoir anticiper les besoins des futurs utilisateurs industriels de COACH. -Deux versions de l’outil seront développées: -\begin{itemize} - \item une version libre qui sans bénéficier de l’environnement complet - intégrée à Magillem (sous Eclipse), intÚgrera des moteurs en entrée et en - sortie pour assurer la compatibilité du code généré avec un flot standard - IP-XACT, - \item une version complÚte à vocation commerciale qui pourra être - personnalisée en fonctions des besoins spécifiques des futurs clients. -\end{itemize} -La société Magillem détient une expertise dans les flots de production -des SoC car depuis plusieurs années elle a réussi avec succÚs à assister les -leaders de ce domaine (STM, NXP, TI, Qualcomm, etc.) dans leur migration vers le -standard IEEE 1685 IP-XACT. -Ainsi sa présence assure que les outils développés dans COACH seront en -adéquation avec les besoins correspondant à ce type de clientÚle. -Magillem a également dans sa clientÚle des systémiers utilisateurs de FPGA -(Thales, Astrium, ESA, etc.) dont les besoins sont différents qui seront -considérés comme les cibles privilégiés du projet. -% -\mysubsubsection{Projet trop académique} -\label{trop:academique} -Le projet a été jugé trop académique. Ceci est un peu corrigé par l'arrivée de -\mds mais l'essentiel du développement reste à la charge des partenaires -académiques. -Ceci s'explique par l'historique du projet qui est né de l'initiative des -partenaires académiques. Index: r/anr.bib =================================================================== --- /anr/anr.bib (revision 386) +++ (revision ) @@ -1,1030 +1,0 @@ -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -%%%%% MDS -%Stuyt Jan, Wolfgang Ecker, Mayer Albrecht, Hustin Serge, Amerijckx Christophe, -%de Paoli Serge and Vaumorin Emmanuel -@inproceedings{mds1, - author = {Kruijtzer Wido, Van der Wolf Pieter, de Kock Erwin and All}, - title = {Industrial IP integration flows based on IP-XACT standards}, - booktitle = {Proceedings of the conference on Design, automation and test in Europe}, - series = {DATE'08}, - year = {2008}, - isbn = {978-3-9810801-3-1}, - location = {Munich, Germany}, - pages = {32--37}, - numpages = {6}, - url = {http://doi.acm.org/10.1145/1403375.1403386}, - doi = {http://doi.acm.org/10.1145/1403375.1403386}, - acmid = {1403386}, - publisher = {ACM}, - address = {New York, NY, USA}, -} - -@misc{mds2, - author = {E. Vaumorin, M. Palus, F. Clermidy and J. Martin}, - title = {SPIRIT IP-XACT Controlled ESL Design Tool Applied to a Network-on-Chip Platform}, - howpublished = {\url{http://www.design-reuse.com/articles/18613/ip-xact-esl-noc.html}}, - year = {2008}, -} - -@misc{socketflow, - author = {L. Maillet-Contoz, R. Lucas and E. Vaumorin}, - title = {SocKET design flow and Application on industrial use cases}, - howpublished = {\url{http://socket.imag.fr/Presentations-socket/Vendredi15/Presentation_flot.pdf}}, - note = {home site: \url{http://socket.imag.fr/}}, - year = {2010}, -} - -@misc{dandr, - author = {Marc van Hintum, Paul Williams}, - title = {The Value of High Quality IP-XACT XML}, - howpublished = {\url{http://www.design-reuse.com/articles/19895/ip-xact-xml.html}}, - year = {2010}, -} - -@techreport{rapport-ministere, - author = {Eric Bant\'egnie, Claude Lepape, Jean-Luc Dormoy}, - title = {Briques g\'en\'eriques du logiciel embarqu\'e}, - year = {2010}, - institution = {Mininist\'ere de l'industrie}, -} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -%%%%% LIP6 -% HPC -@InProceedings{hpc06a, - author = {{M.B. Gokhale and al.}}, - title = {{Promises and Pitfalls of Reconfigurable Supercomputing}}, - booktitle = {Systems and Algorithms, CSREA Press}, - pages = {11-20}, - year = {2006}, -} -@MISC{hpc06b, - author = {{D. Buell}}, - title = {{Programming Reconfigurable Computers}}, - booktitle = {Summer Institute}, - howpublished = {http://gladiator.ncsa.uiuc.edu/PDFs/rssi06/presentations/00\_Duncan\_Buell.pdf}, - year = {2006}, -} -@InProceedings{hpc07a, - author = {{T. Van Court and al.}}, - title = {{ Achieving High Performance with FPGA-Based Computing}}, - booktitle = {Computer, vol. 40, no. 3}, - pages = {50-57}, - month = {mars}, - year = {2007}, -} -@misc{hpc08, - title = {Mitrionics}, - howpublished = {http://www.mitrionics.com/}, - year = {2009}, -} -@misc{hpc09, - title = {Gidel}, - howpublished = {http://www.gidel.com/}, - year = {2009}, -} -@misc{hpc10, - title = {Convey Computer}, - howpublished = {http://www.conveycomputers.com/}, - year = {2009}, -} -@InProceedings{hpc11, - author = {E. El-Araby, I. Gonzalez and T. El-Ghazawi}, - title = {Virtual Architecture and Design Automation for Partial Reconfiguration }, - booktitle = {HPRCTA}, - year = {2008}, -} -@InProceedings{hpc12, - author = {{P. Lysaght and J. Dunlop}}, - title = {Dynamic Reconfiguration of Field Programmable Gate Arrays}, - booktitle = {Field Programmable Logic and Applications, Oxford, England}, - month = {Sept}, - year = {1993}, -} - - -% System design -@misc{soclib, - title = {Soclib}, - howpublished = {http://www.soclib.fr/}, - year = {2009}, -} - -@misc{system-generateur-for-dsp, - title = {{System Generator for DSP}}, - howpublished = {http://www.xilinx.com/tools/sysgen.htm}, - year = {2009}, -} - -@misc{spoc-builder, - title = {{sopc builder support}}, - howpublished = {http://www.altera.com/support/software/system/sopc/sof-sopc\_builder.html}, - year = {2009}, -} - -@InProceedings{cosy, - author = { J.Y Brunel and A. San Giovanni-Vincentelli and R. Krees and W. Kruijtzer }, - title = { COSY: a methodology for system design based on reusable hardware \& software IP's}, - booktitle = { Technologies for the Information Society }, - publisher = { IOS Press }, - year = {1998}, - pages = {709-716}, -} - -@InProceedings{disydent05, - author = {{Ivan Aug\'{e}, Fr\'{e}d\'{e}ric P\'{e}trot, Fran\c{c}ois Donnet and Pascal Gomez}}, - title = {{Platform-based design from parallel C specifications}}, - booktitle = {IEEE Transaction on CAD of Integrated Circuits and Systems}, - pages = {1811--1826}, - month = {December}, - year = {2005}, -} -@inproceedings{dspin08, - author = {Miro-Panades, Ivan and Clermidy, Fabien and Vivet, Pascal and Greiner, Alain}, - title = {Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture}, - booktitle = {NOCS '08: Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip}, - year = {2008}, - isbn = {978-0-7695-3098-7}, - pages = {139--148}, - publisher = {IEEE Computer Society}, - address = {Washington, DC, USA}, - } - - -% HLS -% http://mesl.ucsd.edu/spark/index.shtml -@INBOOK{spark04, - author = {S. Gupta and al.}, - title = {SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits}, - publisher = {Springer}, - year = {2004}, -} - - -@INBOOK{ugh08, - author = {Ivan Aug\'{e} and Fr\'{e}d\'{e}ric P\'{e}trot}, - title = {User Guided High Level Synthesis}, - booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits}, - publisher = {Springer}, - year = {2008}, - chapter = {10}, - pages = {139-148}, -} - %editor = { Philippe Coussy and Adam Moriawiec}, - -@misc{pico, - title = {{PICO}}, - howpublished = {http://www.synfora.com/}, - year = {2009}, -} - -@misc{catapult-c, - title = {{CATAPULT-C Mentor HLS tool}}, - howpublished = {http://www.mentor.com/products/esl/high\_level\_synthesis/}, - year = {2009}, -} - -@misc{cynthetizer, - title = {{Forte's CYNTHESIZER}}, - howpublished = {http://www.forteds.com/}, - year = {2009}, -} - -@inproceedings{IP-XACT-08, - author = {Kruijtzer, Wido and van der Wolf, Pieter and de Kock, Erwin and Stuyt, Jan and Ecker, Wolfgang and Mayer, Albrecht and Hustin, Serge and Amerijckx, Christophe and de Paoli, Serge and Vaumorin, Emmanuel}, - title = {Industrial IP integration flows based on IP-XACT standards}, - booktitle = {Proceedings of the conference on Design, automation and test in Europe}, - series = {DATE '08}, - year = {2008}, - isbn = {978-3-9810801-3-1}, - location = {Munich, Germany}, - pages = {32--37}, - numpages = {6}, - url = {http://doi.acm.org/10.1145/1403375.1403386}, - doi = {http://doi.acm.org/10.1145/1403375.1403386}, - acmid = {1403386}, - publisher = {ACM}, - address = {New York, NY, USA}, -} - - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -%%% UBS - -@INBOOK{IEEEDT, -author = {Philippe Coussy and Andres Takach}, -title = {Special Issue on High-Level Synthesis}, -journal ={IEEE Design and Test of Computers}, -volume = {25},issn = {0740-7475}, -year = {2008}, -pages = {393},doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2008.147}, -publisher = {IEEE Computer Society}, -address = {Los Alamitos, CA, USA},} - - -@BOOK{HLSBOOK, - author = {P. Coussy and A. Morawiec}, - title = {High-Level Synthesis: From Algorithm to Digital Circuits}, - publisher = {Springer}, - year = {2008}, -} - -@BOOK{CATRENE, - author = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics}, - title = {European Roadmap for EDA}, - publisher = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics}, - year = {2009}, -} - -@INBOOK{gaut08, - author = {P. Coussy and al.}, - title = {GAUT: A High-Level Synthesis Tool for DSP applications}, - booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits}, - publisher = {Springer}, - year = {2008}, -} - -@article{DBLP:journals:dt:CoussyT09, - author = {Philippe Coussy and - Andres Takach}, - title = {Guest Editors' Introduction: Raising the Abstraction Level - of Hardware Design}, - journal = {IEEE Design {\&} Test of Computers}, - volume = {26}, - number = {4}, - year = {2009}, - pages = {4-6}, - ee = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.80}, - bibsource = {DBLP, http://dblp.uni-trier.de} -} - - -@article{DBLP:journals:dt:CoussyGMT09, - author = {Philippe Coussy and - Daniel D. Gajski and - Michael Meredith and - Andres Takach}, - title = {An Introduction to High-Level Synthesis}, - journal = {IEEE Design {\&} Test of Computers}, - volume = {26}, - number = {4}, - year = {2009}, - pages = {8-17}, - ee = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.69}, - bibsource = {DBLP, http://dblp.uni-trier.de} -} - - -@article{DBLP:journals:vlsisp:ThabetCHM09, - author = {Farhat Thabet and - Philippe Coussy and - Dominique Heller and - Eric Martin}, - title = {Exploration and Rapid Prototyping of DSP Applications using - SystemC Behavioral Simulation and High-level Synthesis}, - journal = {Signal Processing Systems}, - volume = {56}, - number = {2-3}, - year = {2009}, - pages = {167-186}, - ee = {http://dx.doi.org/10.1007/s11265-008-0235-1}, - bibsource = {DBLP, http://dblp.uni-trier.de} -} - - - -@inproceedings{CHAVET:2007:HAL-00153994:1, - title = { {A} {M}ethodology for {E}fficient {S}pace-{T}ime {A}dapter {D}esign {S}pace {E}xploration: {A} {C}ase {S}tudy of an {U}ltra {W}ide {B}and {I}nterleaver}, - author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric}, - abstract = {{T}his paper presents a solution to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {T}he {RCG} properties enable an efficient architecture space exploration in order to synthesize a {STAR} component. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.}, - language = {{A}nglais}, - affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics }, - booktitle = {{P}roceedings of the {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) {T}he {IEEE} {I}nternational {S}ymposium on {C}ircuits and {S}ystems ({ISCAS}) }, - publisher = {{L}ibrary of {C}ongress }, - pages = {2946 }, - address = {{N}ew {O}rleans {\'E}tats-{U}nis d'{A}m{\'e}rique }, - editor = {{IEEE} }, - note = {{ISBN}:1-4244-0921-7 }, - audience = {internationale }, - day = {28}, - month = {05}, - year = {2007}, - URL = {http://hal.archives-ouvertes.fr/hal-00153994/en/}, - URL = {http://hal.archives-ouvertes.fr/hal-00153994/PDF/ISCAS_Chavet1992.pdf}, -} - - -@inproceedings{DBLP:conf:iccad:ChavetACCJUM07, - author = {Cyrille Chavet and - Caaliph Andriamisaina and - Philippe Coussy and - Emmanuel Casseau and - Emmanuel Juin and - Pascal Urard and - Eric Martin}, - title = {A design flow dedicated to multi-mode architectures for - DSP applications}, - booktitle = {ICCAD}, - year = {2007}, - pages = {604-611}, - ee = {http://doi.acm.org/10.1145/1326073.1326199}, - bibsource = {DBLP, http://dblp.uni-trier.de} -} -%crossref = {DBLP:conf:iccad:2007}, - - -@inproceedings{DBLP:conf:glvlsi:ChavetCUM07, - author = {Cyrille Chavet and - Philippe Coussy and - Pascal Urard and - Eric Martin}, - title = {A design methodology for space-time adapter}, - booktitle = {ACM Great Lakes Symposium on VLSI}, - year = {2007}, - pages = {347-352}, - ee = {http://doi.acm.org/10.1145/1228784.1228868}, - bibsource = {DBLP, http://dblp.uni-trier.de} -} -%crossref = {DBLP:conf:glvlsi:2007}, - - -@inproceedings{CHAVET:2007:HAL-00154025:1, - title = { {A}pplication of a design space exploration tool to enhance interleaver generation}, - author = {{C}havet, {C}yrille and {C}oussy, {P}hilippe and {U}rard, {P}ascal and {M}artin, {E}ric}, - abstract = {{T}his paper presents a methodology to efficiently explore the design space of communication adapters. {I}n most digital signal processing ({DSP}) applications, the overall performance of the system is significantly affected by communication architectures, as a consequence the designers need specifically optimized adapters. {B}y explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named {S}pace-{T}ime {A}dapte{R} ({STAR}). {O}ur design flow inputs a {C} description of {I}nput/{O}utput data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a {R}esource {C}onstraints {G}raph ({RCG}). {D}esign space exploration is then performed through associated tools, to synthesize a {STAR} component under time-to-market constraints. {T}he proposed approach has been tested to design an industrial data mixing block example: an {U}ltra-{W}ideband interleaver.}, - language = {{A}nglais}, - affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {STM}icroelectronics - {STM} - {STM}icroelectronics }, - booktitle = {{P}roceedings of the {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) {E}uropean {S}ignal {P}rocessing {C}onference ({EUSIPCO}-2007) }, - publisher = {{E}urasip }, - pages = {??? }, - address = {{P}oznan {P}ologne }, - audience = {internationale }, - day = {03}, - month = {09}, - year = {2007}, - URL = {http://hal.archives-ouvertes.fr/hal-00154025/en/}, - URL = {http://hal.archives-ouvertes.fr/hal-00154025/PDF/EUSIPCO_chavet.pdf}, -} - - -@inproceedings{ANDRIAMISAINA:2007:HAL-00153086:1, - title = { {S}ynthesis of {M}ultimode digital signal processing systems}, - author = {{A}ndriamisaina, {C}aaliph and {C}asseau, {E}mmanuel and {C}oussy, {P}hilippe}, - abstract = {{I}n this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. {T}he inputs of the design flow are the data flow graphs ({DFG}s), representing the different modes (i.e. the different applications to be implemented), with their respective throughput constraints. {W}hile traditional approaches merge {DFG}s together before the synthesis process, we propose to use ad-hoc scheduling and binding steps during the synthesis of each {DFG}. {T}he scheduling, which assigns operations to specific time steps, maximizes the similarity between the control steps and thus decreases the controller complexity. {T}he binding process, which assigns operations to specific functional units and data to specific storage elements, maximizes the similarity between datapaths and thus minimizes steering logic and register overhead. {F}irst results show the interest of the proposed synthesis flow.}, - language = {{A}nglais}, - affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud - {R}2{D}2 - {INRIA} - {IRISA} - {CNRS} : {UMR}6074 - {INRIA} - {I}nstitut {N}ational des {S}ciences {A}ppliqu{\'e}es de {R}ennes - {E}cole {N}ationale {S}up{\'e}rieure des {S}ciences {A}ppliqu{\'e}es et de {T}echnologie - {U}niversit{\'e} de {R}ennes 1 }, - booktitle = {{P}roceeding of {A}daptive {H}ardware and {S}ystems {NASA}/{ESA} {C}onference on {A}daptive {H}ardware and {S}ystems }, - publisher = {{AHS} }, - pages = {7 }, - address = {{E}dinburgh {R}oyaume-{U}ni }, - audience = {internationale }, - year = {2007}, - URL = {http://hal.archives-ouvertes.fr/hal-00153086/en/}, - URL = {http://hal.archives-ouvertes.fr/hal-00153086/PDF/PID411805.pdf}, -} - - -@inproceedings{COUSSY:2005:HAL-00077301:1, - title = { {A} {M}ore {E}fficient and {F}lexible {DSP} {D}esign {F}low from {MATLAB}-{SIMULINK}}, - author = {{C}oussy, {P}hilippe and {C}orre, {G}wenol{\'e} and {B}omel, {P}ierre and {S}enn, {E}ric and {M}artin, {E}ric}, - abstract = {{T}he design of complex {D}igital {S}ignal {P}rocessing systems implies to minimize architectural cost and to maximize timing performances while taking into account communication and memory accesses constraints for the integration of dedicated hardware accelerator. {U}nfortunately, the traditional {M}atlab/{S}imulink design flows gather not very flexible hardware blocs. {I}n this paper, we present a methodology and a tool that permit the {H}igh-{L}evel {S}ynthesis of {DSP} applications, under both {I}/{O} timing and memory constraints. {B}ased on formal models and a generic architecture, this tool helps the designer in finding a reasonable trade-off between the circuit's latency and its architectural complexity. {T}he efficiency of our approach is demonstrated on the case study of a {FFT} algorithm.}, - keywords = {{DSP} application, synthesis under memory and communication constraints}, - language = {{A}nglais}, - affiliation = {{L}aboratoire d'{E}lectronique des {S}yst{\`e}mes {TE}mps {R}{\'e}el - {LESTER} - {CNRS} : {FRE}2734 - {U}niversit{\'e} de {B}retagne {S}ud }, - booktitle = {{IEEE} {I}nternational {C}onference on {A}coustic, {S}peech and {S}ignal {P}rocessing }, - publisher = {{IEEE} }, - pages = {{V}ol. {V} p. 61-64 }, - editor = {{IEEEE} }, - year = {2005}, - URL = {http://hal.archives-ouvertes.fr/hal-00077301/en/}, - URL = {http://hal.archives-ouvertes.fr/hal-00077301/PDF/coussy_final.pdf}, -} - -@ARTICLE{5605303, - author={Andriamisaina, C. and Coussy, P. and Casseau, E. and Chavet, C.}, - journal={Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, title={High-Level Synthesis for Designing Multimode Architectures}, - year={2010}, - month={nov.}, - volume={29}, - number={11}, - pages={1736 -1749}, - keywords={GAUT;associated high-level synthesis tool;controller complexity;digital signal processing;image processing;joint-scheduling algorithm;monomode architectures;multimode architecture design;single register transfer level hardware architecture;specific binding approach;high level synthesis;reconfigurable architectures;scheduling;}, - doi={10.1109/TCAD.2010.2062751}, - ISSN={0278-0070}, -} - - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -%%%%% IRISA -@InProceedings{KluterCodes08, - author = {{Theo Kluter and Philip Brisk and Paolo Ienne and and Edoardo Charbon}}, - title = {{Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions}}, - booktitle = {ISSS/CODES}, - year = {2008}, -} - -@InProceedings{KluterDAC09, - author = {{Theo Kluter and Philip Brisk and Paolo Ienne and and Edoardo Charbon}}, - title = {{Way Stealing : Cache-assisted Automatic Instruction Set Extensions}}, - booktitle = {Design Automation Conference (DAC)}, - year = {2009}, -} - -@InProceedings{YuCodes04, - author = {{Pan Yu and Tulika Mitra}}, - title = {{Scalable Custom Instructions Identification for Instruction Set Extensible Processors}}, - booktitle = {ISSS/CODES}, - year = {2004}, -} - -@InProceedings{Dinh08, - author = {{Quang Dinh and Deming Chen and Martin D.~F.~Wong}}, - title = {{Efficient ASIP Design for Configurable Processors with Fine-Grained Resource Sharing}}, - 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author = {Christophe Alias and Alain Darte and Alexandru Plesco}, - title = {Optimizing {DDR-SDRAM} Communications at {C}-level for Automatically-Generated Hardware Accelerators. {A}n Experience With the {A}ltera {C2H HLS} Tool}, - booktitle = {IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)}, - year = {2010} -} - -@InProceedings{ca:nuca, - author = {Qingda Lu and Christophe Alias and Uday Bondhugula and Sriram Krishnamoorthy and J. Ramanujam and Atanas Rountev and P. Sadayappan and Yongjian Chen and Haibo Lin and Tin-fook Ngai}, - title = {Data Layout Transformation for Enhancing Locality on {NUCA} Chip Multiprocessors}, - booktitle = {ACM/IEEE Conference on Parallel Architectures and Compilation Techniques (PACT)}, - year = {2009} -} - - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -%%% FC - -@InProceedings{ Martin09c, - author = {Martin, K. and Wolinski, Ch. and Kuchcinski, K. and Floch, A. and Charot, F.}, - title = {Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system}, - address = {Boston, MA, USA}, -month = jul, - year = 2009, -booktitle ={Proc. of the 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors}, -pages = {145-152}, -publisher = {IEEE Computer Society}, - x-proceedings = {yes}, - x-international-audience = {yes}, - x-editorial-board = {yes}, - x-invited-conference = {no}, - x-hal = {no} -} - -@InProceedings{Martin09d, - author = {Martin, K. and Wolinski, Ch. and Kuchcinski, K. and Floch, A. and Charot, F.}, - title = {Constraint-Driven Identification of Application Specific Instructions in the DURASE system}, - booktitle = {Proc. of Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)}, - address = {Samos, Greece}, -month = jul, - year = 2009, -volume = {5657}, -series = {Lecture Notes in Computer Science}, -pages = {194-203}, -publisher = {Springer}, - x-proceedings = {yes}, - x-international-audience = {yes}, - x-editorial-board = {yes}, - x-invited-conference = {no}, - x-hal = {no} -} -@InProceedings{ Wolinski09a, - author = {Wolinski, Ch. and Kuchcinski, K. and Raffin, E. and Charot, F.}, - title = {Architecture-Driven Synthesis of Reconfigurable Cells}, -booktitle = {{Proc. of the 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD)}}, - address = {Patras, Greece}, -month = sep, - year = 2009, -pages = {531 - 538 }, -doi={10.1109/DSD.2009.183}, - x-proceedings = {yes}, - x-international-audience = {yes}, - x-editorial-board = {yes}, - x-invited-conference = {no}, - x-hal = {no} -} -@inproceedings{RAFFIN:2010:INRIA-00539874:1, - HAL_ID = {inria-00539874}, - URL = {http://hal.inria.fr/inria-00539874/en/}, - title = { {S}cheduling, {B}inding and {R}outing {S}ystem for a {R}un-{T}ime {R}econfigurable {O}perator {B}ased {M}ultimedia {A}rchitecture}, - author = {{R}affin, {E}rwan and {W}olinski, {C}hristophe and {C}harot, {F}ran{\c{c}}ois and {K}uchcinski, {K}rzysztof and {G}uyetant, {S}t{\'e}phane and {C}hevobbe, {S}t{\'e}phane and {C}asseau, {E}mmanuel}, - booktitle = {Conference on {D}esign and {A}rchitectures for {S}ignal and {I}mage {P}rocessing ({DASIP} 2010)}, - address = {{E}dinburgh {R}oyaume-{U}ni }, - audience = {internationale }, - month = oct, - year = {2010}, - URL = {http://hal.inria.fr/inria-00539874/PDF/dasip2010.pdf}, - x-hal={inria-00539874}, -} - -@INBOOK{sd:mmalpha, - chapter = {High-Level Synthesis of Loops Using the Polyhedral Model: The MMAlpha Software}, - pages = {215-230}, - title = {High-Level Synthesis From Algorithm to Digital Circuit}, - publisher = {Springer Netherlands}, - year = {2008}, - editor = {Philippe Coussy and Adam Morawiec}, - author = {Steven Derrien and Sanjay Rajopadhye and Patrice Quinton and Tanguy Risset}, - doi = {10.1007/978-1-4020-8588-8}, - x-international-audience = {yes}, - x-editorial-board = {yes}, - x-proceedings = {yes}, - x-hal = {no} -} - - -@article{sd:rdisk, - author= {Stéphane Guyetant and Mathieu Giraud and Ludovic L'Hours and Steven Derrien and Stephane Rubini and Dominique Lavenier and Frédéric Raimbault }, - title= {{Cluster of Reconfigurable Nodes for Scanning Large Genomic Banks}}, - journal= {Parallel Computing}, - year ={2005} -} - -@inproceedings{sd:lomita, - author= {M. Adeel Pasha and Steven Derrien and Olivier Sentieys}, - title= {{A complete design-flow for the generation of ultra low-power wsn node architectures based on micro- tasking}}, - booktitle = {Proceedings of the IEEE/ACM Design Automation Conference}, - year= {2010} -} - -@article{sd:hmmer, - author= {Steven Derrien and Patrice Quinton}, - title= {{ Hardware Acceleration of HMMER on FPGAs}}, - journal= {Journal of Signal Processing Systems }, - year ={2010}, -} Index: r/anr.sty =================================================================== --- /anr/anr.sty (revision 386) +++ (revision ) @@ -1,340 +1,0 @@ -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\newlength{\desclen} -\newlength{\yearlen} -\newlength{\mmlen} - -\newbox\livrable@box -\newbox\tmp@box - -\let\specHasManual\relax -\let\specCsgManual\relax - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\def\eoa{end-of-args} -\def\@@novers#1-#2\eoa{#1} -\def\@novers#1{\ifx\relax#1\def\next{{\color{red}FIXME}}\else\def\next{\expandafter\@@novers#1\eoa}\fi\next} - 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\ifx\MDS\disable\let\MDS\enable\fi% -\fi% -\def\@leader{\begin{small}\textcolor{red}{lead.}\end{small}} -\def\@partner{\begin{small}\textcolor{blue}{part.}\end{small}} -\def\@INRIA{\ifx\INRIA\disable{}\else\ifx\INRIA\enable{\@partner}\else{\@leader}\fi\fi}% -\def\@LIP{\ifx\LIP\disable{}\else\ifx\LIP\enable{\@partner}\else{\@leader}\fi\fi}% -\def\@UPMC{\ifx\UPMC\disable{}\else\ifx\UPMC\enable{\@partner}\else{\@leader}\fi\fi}% -\def\@TIMA{\ifx\TIMA\disable{}\else\ifx\TIMA\enable{\@partner}\else{\@leader}\fi\fi}% -\def\@UBS{\ifx\UBS\disable{}\else\ifx\UBS\enable{\@partner}\else{\@leader}\fi\fi}% -\def\@BULL{\ifx\BULL\disable{}\else\ifx\BULL\enable{\@partner}\else{\@leader}\fi\fi}% -\def\@THALES{\ifx\THALES\disable{}\else\ifx\THALES\enable{\@partner}\else{\@leader}\fi\fi}% -\def\@MDS{\ifx\MDS\disable{}\else\ifx\MDS\enable{\@partner}\else{\@leader}\fi\fi}% -\begin{tabular}{|c|c|c|c|c|c|c|c|}\hline -\Smds & \Supmc & \Subs & \Slip & \Stima & \Sinria & \Sbull & \Sthales \\\hline -\@MDS & \@UPMC & \@UBS & \@LIP & \@TIMA & \@INRIA & \@BULL & \@THALES \\\hline -\end{tabular}\par -} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\newenvironment{objectif}% -{\begin{description}\item[Objectives]} -{\end{description}} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\newcount\taskcnt\taskcnt=0 -\newcount\subtaskcnt -\newcount\livrablecnt - - \def\@subtask#1{% - \global\advance\subtaskcnt1 - \def\subtaskname{S\taskname-\the\subtaskcnt}% - \write@ganttdata{STN=\the\taskcnt\space\the\subtaskcnt\space#1}% - \item[\subtaskname: #1]% - \IfFileExists{tmp/st\the\taskcnt-\the\subtaskcnt-partner.tex}% - {(\input{tmp/st\the\taskcnt-\the\subtaskcnt-partner.tex})}% - {\message{SKIPPING tmp/st\the\taskcnt-\the\subtaskcnt-partner.tex files}}% - \mbox{}\\% -} - -\newenvironment{workpackage}{% - \global\advance\taskcnt1% - \global\subtaskcnt0% - \def\taskname{T\the\taskcnt}% - \begin{description}% - \let\subtask\@subtask% -}{ \end{description}} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\def\writeganttinfo#1#2#3#4#5#6{% - \write@ganttdata{% - L=1 T=\the\taskcnt\space S=\the\subtaskcnt\space% - D=\the\livrablecnt\space V=\vers\space% - BM=#1 EM=#2 R=#3 PART={#4} KIND={#5} TITLE=#6% - }% -} - -\def\livrable@description@width{13.5cm} -\def\livrable@description@width{10.4cm} -\newif\if@livrable@firsttable@ -\newif\if@livrable@table@MustBeOpened@ -\newif\if@livrable@table@MustBeClosed@ -\newif\if@livrable@table@MustBeClosed@after@ -\let\librable@table@print@addon\relax -\def\livrable@table@begin{\begin{tabular}{|p{3.5em}|c|c|c|l|}\hline} -\def\livrable@table@line#1#2#3#4#5#6{ - \makebox[3.5em][c]{\begin{small}#1\end{small}} & - \makebox[2.2em]{\begin{small}#2\end{small}} & - \makebox[1.5em]{\begin{small}#3\end{small}} & - \makebox[2.2em]{\begin{small}#4\end{small}} & - #5\\#6} -\def\livrable@table@end{\end{tabular}\\} -\def\livrable@print@table{% - \if@livrable@table@MustBeOpened@% - \livrable@table@begin% - \global\@livrable@table@MustBeOpened@false% - \fi% - \if@livrable@firsttable@% - \livrable@table@line{number}{date}{type}{resp.}{description}{\hline\hline}% - \fi% - \global\@livrable@firsttable@false% - \livrable@table@line% - {\textsc{\name}}% - {\textsc{T0+\livrableEndDate}}% - {\textsc{\livrableType}}% - {\textsc{\livrableLeader}}% - %{\mbox{\copy\livrable@box}}{\hline}% - %{\raisebox{\@hypertarget@cor}[\ht\livrable@box][\ht\livrable@box]{\copy\livrable@box}\librable@table@print@addon\vspace*{1pt}}{\hline}% - {\raisebox{\@hypertarget@cor}{\copy\livrable@box}\librable@table@print@addon\vspace*{1pt}}{\hline}% -% {}{\cline{2-5}}% -% %& \multicolumn{4}{l|}{\raisebox{\@hypertarget@cor}{\copy\livrable@box}}\\\hline% -% & \multicolumn{4}{l|}{{\copy\livrable@box}}\\\hline% - \if@livrable@table@MustBeClosed@% - \livrable@table@end% - \global\@livrable@table@MustBeOpened@true% - \global\@livrable@table@MustBeClosed@false% - \fi% - \if@livrable@table@MustBeClosed@after@% - \global\@livrable@table@MustBeClosed@true% - \global\@livrable@table@MustBeClosed@after@false% - \fi% - \global\def\@hypertarget@cor{0pt}% - \global\let\librable@table@print@addon\relax% -} - -\def\@livrable@desc@box@start{% - \begin{lrbox}{\livrable@box}\begin{minipage}[t]{\livrable@description@width}% - \fontsize{11.0pt}{10pt}\selectfont% - \let\ia@description\description% - \def\description{\vspace*{-0.0ex}\ia@description\itemsep=1pt\topsep2pt\parskip0pt}% - %\let\ia@enddescription\enddescription% - %\newenvironment{description}{% - %}{\ia@enddescription}% -} - -\def\@livrable@desc@box@start@eatCR#1{\@livrable@desc@box@start#1} -%\def\tmp{ -%} -%\def\eat{\message{AAAAAAAAAAAAA:EAT}\@livrable@desc@box@start} -%\if\noexpand\nexttok\tmp -% \message{AAAAAAAAAAAAAAAAAAAAA:OUI}% -% \def\cont{\eat}% -%\else% -% \message{AAAAAAAAAAAAAAAAAAAAA:NON}% -% \def\cont{\@livrable@desc@box@start}% -%\fi% -%\cont} - - -\def\@itemV@next#1#2#3#4#5{\livrable@print@table\@itemV@first{#1}{#2}{#3}{#4}{#5}} -\def\@itemV@first#1#2#3#4#5{% - \def\vers{V\the\verscnt}% - \global\edef\name{D\the\taskcnt\the\subtaskcnt\the\livrablecnt-\vers}% - \global\def\librable@table@print@addon{\hypertarget{\name}{}}% - \gdef\livrableEndDate{#2}% - \gdef\livrableType{#3}% - \gdef\livrableLeader{#4}% - \def\itemV{\end{minipage}\end{lrbox}\global\advance\verscnt1\global\setbox\livrable@box=\copy\livrable@box\@itemV@next}% - \def\itemL{\end{minipage}\end{lrbox}\global\advance\verscnt1\global\setbox\livrable@box=\copy\livrable@box\@itemL@next}% - \writeganttinfo{#1}{#2}{none}{#4}{#3}{#5}% - \futurelet\nexttok\@livrable@desc@box@start@eatCR% -} -% \parskip0pt \topsep0pt \parsep0pt \itemsep0pt \partopsep0pt - -\def\@itemL@next#1#2#3#4#5#6{\global\@livrable@table@MustBeClosed@after@true\livrable@print@table\@itemL@first{#1}{#2}{#3}{#4}{#5}{#6}} -\def\@itemL@first#1#2#3#4#5#6{% - \def\vers{VF}% - \global\edef\name{D\the\taskcnt\the\subtaskcnt\the\livrablecnt-\vers}% - \global\def\librable@table@print@addon{\hypertarget{\name}{}\hypertarget{\expandafter\@@novers\name\eoa}{}}% - \gdef\livrableEndDate{#2}% - \gdef\livrableType{#3}% - \gdef\livrableLeader{#4}% - \def\itemV{\end{minipage}\end{lrbox}\global\advance\livrablecnt1\global\verscnt1\global\setbox\livrable@box\copy\livrable@box\@itemV@next}% - \def\itemL{\end{minipage}\end{lrbox}\global\advance\livrablecnt1\global\verscnt1\global\setbox\livrable@box\copy\livrable@box\@itemL@next}% - \writeganttinfo{#1}{#2}{#6}{#4}{#3}{#5}% - %\gdef\baselinestretch{2.50}XXX\\% - \global\@livrable@table@MustBeClosed@true - \futurelet\nexttok\@livrable@desc@box@start@eatCR% -} - -\newenvironment{livrable}{% - \newcount\verscnt\verscnt=1 - \livrablecnt0 - \def\livrableTableDef{\begin{tabular}{|p{3.5em}|c|c|c|p{.625\linewidth}|}\hline} - \ifvmode \else\par\fi -\def\OtherPartner##1##2##3##4##5{{% -\let\xcoach\relax% -\let\xcoachplus\relax% -\let\inria\relax\let\Sinria\relax% -\let\lip\relax\let\Slip\relax% -\let\tima\relax\let\Stima\relax% -\let\ubs\relax\let\Subs\relax% -\let\upmc\relax\let\Supmc\relax% -\let\altera\relax\let\Saltera\relax% -\let\bull\relax\let\Sbull\relax% -\let\thales\relax\let\Sthales\relax% -\let\mds\relax\let\Smds\relax% -\immediate\write\ganttdata{% - L=0 T=\the\taskcnt\space S=\the\subtaskcnt\space% - D=\the\livrablecnt\space BM=##1 EM=##2 R=##4 PART={##3} TITLE=% -}% -}##5} - \let\itemV\@itemV@first - \let\itemL\@itemL@first - \@livrable@firsttable@true - \@livrable@table@MustBeOpened@true - \@livrable@table@MustBeClosed@false - \@livrable@table@MustBeClosed@after@false - \def\@hypertarget@cor{0pt} -}{% - \end{minipage}\end{lrbox}\global\setbox\livrable@box=\copy\livrable@box% - \@livrable@table@MustBeClosed@true\livrable@print@table% -} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Index: /anr/anr.tex =================================================================== --- /anr/anr.tex (revision 386) +++ /anr/anr.tex (revision 1) @@ -1,6 +1,6 @@ -\documentclass[11pt,a4paper]{article} +\documentclass[12pt,a4paper]{article} -\usepackage[french,english]{babel} -\usepackage[utf8x]{inputenc} +\usepackage[french]{babel} +%\usepackage[utf8x]{inputenc} \usepackage{times} \usepackage[T1]{fontenc} @@ -10,312 +10,12 @@ \usepackage{xmpmulti} \usepackage{graphicx} -\usepackage{color} -\usepackage{xspace} -\usepackage{geometry} -\usepackage{textcomp} -\usepackage{multirow} -\usepackage{lscape} -\geometry{verbose,a4paper,tmargin=3cm,bmargin=2cm,lmargin=2cm,rmargin=2cm} -\usepackage{hyperref} -\hypersetup{ - %backref=true, - %pagebackref=true, - %hyperindex=true, - colorlinks=true, %colorise les liens - breaklinks=true, %permet le retour à la ligne dans les lien - urlcolor= blue, %couleur des hyperliens - linkcolor= blue %couleur des liens internes -} -\usepackage{fancybox} -\usepackage{marginnote} - \reversemarginpar - \renewcommand*{\raggedrightmarginnote}{\centering} - \renewcommand*{\marginfont}{\color{blue}\sffamily} - \def\note#1{\marginnote{#1}\label{note:#1}} - \def\seenote#1{#1 (page~\pageref{note:#1})\xspace} -%\usepackage{array} -\usepackage{anr} -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\usepackage{fancyhdr} -\usepackage{lastpage} -\pagestyle{fancy} -\lhead{\begin{minipage}{1.5cm}\includegraphics[width=\linewidth]{logo-anr}\vspace*{1mm}\end{minipage}} -\chead{\begin{minipage}{8cm}\small\center Programme Ing\'enierie num\'erique -\& s\'ecurit\'e\\Edition 2011\vspace*{1mm}\end{minipage}} -\rhead{\begin{minipage}{5cm}\small\raggedleft Project COACH\\Document -scientifique\vspace*{1mm}\end{minipage}} -\lfoot{\begin{minipage}{7cm}\small ANR-GUI-AAP-04 – Doc Scientifique 2011\end{minipage}} -\cfoot{\begin{minipage}{5cm}\end{minipage}} -\rfoot{\begin{minipage}{2cm}\small\center\thepage/\pageref{LastPage}\end{minipage}} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\def\xcoach{\texttt{xcoach}\xspace} -\def\xcoachplus{\texttt{xcoach+}\xspace} -\def\backbone{backbone infrastructure\xspace} -\def\Backbone{Backbone infrastructure\xspace} -\def\hommemoislong{men$\ast$months\xspace} -\def\hommemois{m.m\xspace} -\def\xilinxcpu{ARM\xspace} -\def\xilinxbus{AMBA\xspace} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\def\anrdoc#1{} -\let\pagefeed\relax -\def\euro{\mbox{\raisebox{.25ex}{{\it =}}\hspace{-.5em}{\sf C}}} -\definecolor{gris}{gray}{0.55} -\definecolor{rouge}{rgb}{1.0,0.2,0.2} -\def\mustbecompleted#1{} -\def\parlf{\mbox{}\vspace*{1.0ex}\\} -\def\ADDED#1{\textcolor{blue}{#1}} -\newenvironment{ADDEDENV}{\color{blue}}{} -\def\SUPPRESSED#1{\textcolor{gris}{#1}} -\newenvironment{SUPPRESSEDENV}{\color{gris}}{} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\def\Sformat#1{\begin{small}\textsc{#1}\end{small}} -\def\inria{INRIA\xspace} \def\Sinria{\Sformat{INRIA}\xspace} -%\def\irisa{INRIA/\-CAIRN\xspace} \def\Sirisa{\Sformat{INRI}\xspace} -\def\liplong{ENS Lyon/LIP/Compsys\xspace} -\def\lip{ENS Lyon\xspace} \def\Slip{\Sformat{LIP}\xspace} -\def\tima{TIMA\xspace} \def\Stima{\Sformat{TIMA}\xspace} -\def\ubs{LAB-STICC\xspace} \def\Subs{\Sformat{UBS}\xspace} -\def\upmc{LIP6\xspace} \def\Supmc{\Sformat{LIP6}\xspace} -\def\bull{BULL\xspace} \def\Sbull{\Sformat{BULL}\xspace} -\def\thales{THALES\xspace} \def\Sthales{\Sformat{TRT}\xspace} \let\TRT\thales -\def\mdslong{MAGILLEM DESIGN SERVICES\xspace} -\def\mds{MAGILLEM\xspace} \def\Smds{\Sformat{MDS}\xspace} - -\def\altera{ALTERA\xspace} \def\Saltera{\Sformat{ALTE}\xspace} -\def\xilinx{XILINX\xspace} \def\Sxilinx{\Sformat{XILX}\xspace} - -\def\alllabs{\inria \citi \lip \tima \ubs \upmc} -\def\allcompagnies{\bull \thales \mds\xspace} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\def\ST{sub-task\xspace} -\def\STs{sub-tasks\xspace} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -% DEBUT CONFIG -% Comment next marcro to suppress the printing of anr directives -% \def\anrdoc#1{\noindent\begin{scriptsize}\textcolor{red}{#1}\end{scriptsize}\ifhmode\par\fi} -% Comment the next macro to suppress the pagefeed -%\let\pagefeed\newpage -% Comment the next macro to suppress it -\def\mustbecompleted#1{\textcolor{red}{#1}} -% FIN CONFIG -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\sloppy - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\begin{document} -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -% 1 -\anrdoc{ -Ce document, hors annexes, ne doit pas dépasser 40 pages, corps de texte en -police de taille 11. Ce point constitue un critÚre de recevabilité de la -proposition de projet. Les propositions de projets ne satisfaisant pas aux -critÚres de recevabilité ne seront pas évaluées. +\title{% +\textbf{COACH:} +\textbf{C}onception d'\textbf{A}rchitecture par +\textbf{C}ompilation et synt\textbf{H}èse } -\def\boitecochee{\fcolorbox{black}{black}{\makebox(0.20,0.20){}}} -\noindent -\begin{tabular}{|p{5cm}|p{10cm}|}\hline -Acronym of the proposal & COACH \\\hline -Title of the proposal in French & - \textbf{C}onception d'\textbf{A}rchitecture sur FPGA par - \textbf{C}ompilation et synt\textbf{H}\`{e}se\\\hline -\begin{minipage}{\linewidth}Title of the proposal in\\ English\end{minipage} - & Architecture Design on FPGA by Compilation and Synthesis \\\hline -\begin{minipage}{\linewidth}Theme\\\end{minipage} - & \setlength{\unitlength}{5.0mm}\begin{picture}(20,2) - \put( 0.5,0.9){\framebox(0.6,0.6){ }} \put( 1.5,0.9){1} - \put( 3.5,1.1){\boitecochee} \put( 4.5,0.9){2} - \put( 6.5,0.9){\framebox(0.6,0.6){}} \put( 7.5,0.9){3} - \put( 9.5,0.9){\framebox(0.6,0.6){ }} \put(10.5,0.9){4} - \put(12.5,0.9){\framebox(0.6,0.6){$\bullet$}} \put(13.5,0.9){5} - \put( 0.5,0){\mbox{{\scriptsize $\bullet$: secondary theme}}} - \end{picture}\\\hline -\begin{minipage}{\linewidth}\mbox{}\\Type of research\\\end{minipage} - & \begin{minipage}{\linewidth} - \setlength{\unitlength}{5.0mm}\begin{picture}(20,3.2) - \put(0.5,0.2){\framebox(0.6,0.6){ }} \put(1.5,0.2){Basic Research} - \put(0.5,1.4){\boitecochee} \put(1.5,1.2){Industrial Research} - \put(0.5,2.2){\framebox(0.6,0.6){ }} \put(1.5,2.2){Experimental Development} - \end{picture}\end{minipage}\\\hline -%Type of scientific project & \setlength{\unitlength}{5.0mm}\begin{picture}(20,1) -% \put(0.5,0){\framebox(0.6,0.6){ }} \put(1.5,0){Platform} -% \end{picture}\\\hline -\end{tabular}\vspace{.5ex}\\ -\begin{tabular}{|c|c|c|c|}\hline - \begin{minipage}{4cm}\center - \vspace*{0.5ex}Total requested \\ funding - \end{minipage} - & \makebox[3cm]{ 999399.88 \euro} - & \begin{minipage}{4.15cm}\center Project Duration \end{minipage} - & \begin{minipage}{3cm}\center 36 months \end{minipage} \\\hline -\end{tabular} -% -\setcounter{tocdepth}{2} -\tableofcontents - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -% 1 -\section{Executive summary} -\anrdoc{Recopier le résumé utilisé dans le document administratif et financier -(dit document de soumission)\\ -De memoire, la taille etait donnee en mot nots, et on avait ete oblige -de raccourcir enormement.} -\input{section-1} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -% 2 -\pagefeed\section{Context and relevance to the call } -\anrdoc{A titre indicatif: de 5 à 10 pages pour ce chapitre\\ -Présentation générale du problÚme qu¿il est proposé de traiter dans le -projet et du cadre de travail (recherche fondamentale, industrielle ou -développement expérimental).} -\input{section-2} - -% 2.1 -\pagefeed\subsection{Context, social and economic issues}\input{section-issues} - -% 2.2 -\pagefeed\subsection{Position of the project}\input{section-position.tex} - -% 2.3 -\pagefeed\subsection{State of the Art}\input{section-etat-de-art} - -% 2.4 -\pagefeed\subsection{Objectives, originality and novelty of the project} -\input{section-objectif.tex} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -% 3 -\section{Scientific and technical objectives / project description} -\anrdoc{A titre indicatif: de 8 à 12 pages pour ce chapitre, en fonction -du nombre de taches.} - -% 3.1 -\pagefeed\subsection{Scientific programme, project structure} -\input{section-project-description.tex} - -% 3.2 -\pagefeed\subsection{Project management} -\input{section-project-management.tex} - -% 3.3 -\pagefeed\subsection{Description by task} -\label{task-description} -\anrdoc{Pour chaque tâche, décrire:\begin{itemize} -\item les objectifs de la tâche et éventuels indicateurs de succÚs, -\item le responsable de la tâche et les partenaires impliqués (possibilité -de l'indiquer sous forme graphique), -\item le programme détaillé des travaux par tâche, -\item les livrables de la tâche, -\item les contributions des partenaires (le «qui fait quoi»), -\item la description des méthodes et des choix techniques et de la maniÚre -dont les solutions seront apportées, -\item les risques de la tâche et les solutions de repli envisagées. -\end{itemize}} -In this document, we use the following abbreviations in the tables and Gantt diagrams: -\begin{description} - \item[partner] - \Sinria for \inria, \Slip for \liplong, \Stima for \tima, \Subs for \ubs, - \Supmc for \upmc, \Sbull for \bull, \Sthales for \thales, - and \Smds for \mds. - \item[kind of the deliverable] - \texttt{x} for a software, \texttt{d} for a document and \texttt{h} for a hardware - component. - \item[task contribution] - "{\color{red}lead.}" for leader and - "{\color{blue}part.}" for participant. - \item[other abbreviations] "resp." for responsible patrner, "kd" for kind of - deliverable. -\end{description} - -\subsubsection{Task 1: \textit{Project management}} \input{task-management.tex} -\subsubsection{Task 2: \textit{\Backbone}} \input{task-backbone.tex} -\subsubsection{Task 3: \textit{System generation}} \input{task-csg.tex} -\subsubsection{Task 4: \textit{HAS front-end}} \input{task-frontend} -\subsubsection{Task 5: \textit{HAS back-end}} \input{task-backend.tex} -\subsubsection{Task 6: \textit{PC/FPGA communication middleware}}\input{task-hpc} -\subsubsection{Task 7: \textit{Industrial demonstrators}} \input{task-demonstrator.tex} -\subsubsection{Task 8: \textit{Dissemination}} \input{task-dissemination.tex} - -% 3.4 -\subsection{Tasks schedule, deliverables and milestones} -\input{section-project-task-schedule.tex} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\section{Dissemination and exploitation of results. Intellectual property} -\input{section-dissemination.tex} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\section{Consortium Description} -\anrdoc{A titre indicatif: de 2 à 5 pages pour ce chapitre, en fonction du -nombre de partenaires} - -\subsection{Partners description \& relevance, complementarity} -\input{section-consortium-desc.tex} - -\subsection{Relevant experience of the project coordinator} -\input{section-consortium-leader.tex} - -\subsection{Qualification and contribution of each partner} -\input{section-consortium-people.tex} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\section{Scientific justification for the mobilisation of the resources} -\input{section-ressources.tex} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -%\appendix -\newpage -\section{Annexes} -% % % % % % % % % % % % % % % % % % % % % % % % -\subsection{Bibliography} -%\subsection{References} -\anrdoc{Inclure la liste des références bibliographiques utilisées dans la -partie \og état de l'art\fg et les références bibliographiques des -partenaires ayant trait au projet.} -\bibliographystyle{plain} -\bibliography{anr} - -% % % % % % % % % % % % % % % % % % % % % % % % -\newpage\subsection{CV, resume}\input{annexe-cv.tex} -\begin{landscape} -\newpage\subsection{Staff involvement in other contracts}\input{annexe-autre-participation.tex} -\end{landscape} -\newpage\subsection{Man power by partners and by deliverables} -\label{effort:by:partner:livrable} - \subsubsection{Partner 1: \mds} \label{table-livrables-mds} \input{table_mds_full.tex} - \subsubsection{Partner 2: \upmc} \label{table-livrables-upmc} \input{table_upmc_full.tex} - \subsubsection{Partner 3: \ubs} \label{table-livrables-ubs} \input{table_ubs_full.tex} - \subsubsection{Partner 4: \liplong} \label{table-livrables-inria_compsys} \input{table_inria_compsys_full.tex} - \subsubsection{Partner 5: \tima} \label{table-livrables-tima} \input{table_tima_full.tex} - \subsubsection{Partner 6: \inria} \label{table-livrables-inria_cairn} \input{table_inria_cairn_full.tex} - \subsubsection{Partner 7: \bull} \label{table-livrables-bull} \input{table_bull_full.tex} - \subsubsection{Partner 8: \thales} \label{table-livrables-thales} \input{table_thales_full.tex} -\newpage\subsection{Effort tables} -\label{effort:by:livrable} -%\begin{small} -\noindent\input{tmp/effort-par-livrable-1.tex} -\newpage\noindent\input{tmp/effort-par-livrable-2.tex} -\newpage\noindent\input{tmp/effort-par-livrable-3.tex} -\newpage\noindent\input{tmp/effort-par-livrable-4.tex} -%\end{small} - -\newpage\subsection{Letters of interest} -\label{lettre-soutien} -\input{tmp/anr-supporter.tex} - -\newpage\subsection{Prise en compte de l'évaluation 2010} -\input{annexe-reponse.tex} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\begin{document} +\input{body.tex} \end{document} -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Index: r/architecture-csg.fig =================================================================== --- /anr/architecture-csg.fig (revision 386) +++ (revision ) @@ -1,140 +1,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5b -Landscape -Center -Metric -Letter -100.00 -Single --2 -1200 2 -6 3892 1126 5532 2807 -5 1 0 2 0 7 50 -1 -1 0.000 0 1 1 0 4886.631 1711.404 4857 2042 5139 1927 5211 1641 - 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CONTEXTE ET POSITIONNEMENT DU PROJET +% (1 page maximum) Présentation générale du problème qu'il est proposé de traiter +% dans le projet et du cadre de travail (recherche fondamentale, industrielle ou +% développement expérimental). +\end{verbatim} +\end{scriptsize} +An embedded system is an application integrated into one or several chips +in order to accelerate it or to embedd it into a small device such as a personal +digital assistant (PDA). +This topic is investigated since 80s using Applications Specific Integrated Circuits (ASIC), +Digital Signal Processing (DSP) and parallel computing on multiprocessor machines or networks. +More recently, since end of 90s, other technologies appeared like Very Large Instruction Word (VLIW), +Application Specific Instruction Processors (ASIP), System on Chip (SoC), +Multi-Processors SoC (MPSoC). +\\ +During these last decades embedded system was reserved to major industrial companies targeting high volume market +due to the design and fabrication costs. +Nowadays Field Programmable Gate Arrays (FPGA), like Virtex5 from Xilinx and Stratix4 from Altera, +can implement a SoC with multiple processors and several coprocessors for less than 10K euros the piece. +In addition, High Level Synthesis (HLS) becomes more mature and allows to automize design +and to decrease drastically its cost in terms of man power. Thus, both FPGA and HLS tends to spread over +HPC for small companies targeting low volume markets. +\par +To get an efficient embedded system, designer has to take into account application characteristics when it +chooses one of the former technologies. +This choice is not easy and in most cases designer has to try different technologies to retain the +most adapted one. +\\ +The first objective of COACH is to provide an open-source framework to design embedded system +on FPGA device. +COACH framework allows designer to explore various software/hardware partitions of the +target application, to run timing and functional simulations and to generate automatically both +the software and the synthesizable description of the hardware. +The main topics of the project are: +\begin{itemize} +\item +Design space exploration: It consists in analysing the application runnig on FPGA, defining the target +technology (SoC, MPSoC, ASIP, ...) and hardware/software partitioning of tasks depending on +technology choice. This exploration is driven basically by throughput, latency and power consumption +criteria. +\item +Micro-architectural exploration: When hardware components are required, the HLS tools of the framework +generate them automatically. At this stage the framework provides various HLS tools allowing the +micro-architectural space design exploration. The exploration criteria are also throughput, latency +and power consumption. +% FIXME +%CA At this stage, preliminary source-level transformations will be +%CA required to improve the efficiency of the target component. +%CA COACH will also provide such facilities, such as automatic parallelization +%CA and memory optimisation. +\item +Performance measurement: For each point of design space exploration, metrics of criteria are available +such as throughput, latency, power consumption, area, memory allocation and data locality. +They are evaluated using virtual prototyping, estimation or analysing methodologies. +\item +Targeted hardware technology: The COACH description of system is independent of the FPGA family. +Every point of the design exploration space can be implemented on any FPGA having the required resources. +Basically, COACH handles both Altera and Xilinx FPGA families. +\end{itemize} +As an extension of embedded system design, COACH deals also with High Performance Computing (HPC). +In HPC, the kind of targeted application is an existing one running on PC. COACH helps designer +to accelerate it by migrating critical parts into a SoC implemented on a FPGA plugged to the PC bus. +\par +COACH is the result of the will of several laboratory to unify their know how and skills in the +following domains: Operating system and hardware communication (TIMA, SITI), SoC and MPSoC (LIP6 and TIMA), +ASIP (IRISA) and HLS (LIP6, Lab-STIC and LIP). The project objective is to integrate these various +domains into a unique free framework (licence ...) masking as much as possible these domains and its +different tools to the user. + + +\subsection{Economical context and interest} +\hspace{2cm}\begin{scriptsize}\begin{verbatim} +% 1.1. CONTEXTE ET ENJEUX ECONOMIQUES ET SOCIETAUX +% (2 pages maximum) +% Décrire le contexte économique, social, réglementaire. dans lequel se situe +% le projet en présentant une analyse des enjeux sociaux, économiques, environnementaux, +% industriels. Donner si possible des arguments chiffrés, par exemple, pertinence et +% portée du projet par rapport à la demande économique (analyse du marché, analyse des +% tendances), analyse de la concurrence, indicateurs de réduction de coûts, perspectives +% de marchés (champs d'application, .). Indicateurs des gains environnementaux, cycle +% de vie. +\end{verbatim} +\end{scriptsize} +Microelectronic allows to integrate complicated functions into products, to increase their +commercial attractivity and to improve their competitivity. Multimedia and communication +sectors have taken advantage from microelectronics facilities thanks to developpment of +design methodologies and tools for real time embedded systems. Many other sectors could +benefit from microelectronics if these methologies and tools are adapted to their features. +The Non Recurring Engineering (NRE) costs involded in designing and manufacturing an ASIC is +very high. It costs several milliars of euros for IC factory and several millions to fabricate +a specific circuit for example a conservative estimate for a 65nm ASIC project is 10 million USD. +Consequently, it is generally unfeasible to design and fabricate ASICs in +low volumes and ICs are designed to cover a broad applications spectrum at the cost of +performance degradation. +\\ +Today, FPGAs become important actors in the computational domain that was originally dominated +by microprocessors and ASICs. Just like microprocessors FPGA based systems can be reprogrammed +on a per-application basis. At the same time, FPGAs offer significant performance benefits over +microprocessors implementation for a number of applications. Although these benefits are still +generally an order of magnitude less than equivalent ASIC implementations, low costs +(500 euros to 10K euros), fast time to market and flexibility of FPGAs make them an attractive +choice for low-to-medium volume applications. +Since their introduction in the mid eighties, FPGAs evolved from a simple, +low-capacity gate array technology to devices (Altera STRATIX III, Xilinx Virtex V) that +provide a mix of coarse-grained data path units, memory blocks, microprocessor cores, +on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement +complex systems like multi-processors platform with application dedicated coprocessors. +Table~\ref{fpga_market} shows the estimation of FPGA worldwide market in the next years covering +various application domains. The ``high end'' lines concern only FPGA with high logic capacity able +to implement complex systems. +This market is in significant expansion and is estimated to 914 M\$ in 2012. +Using FPGA limits the NRE costs to design cost. This boosts the developpment of methodologies +and tools to automize design and reduce its cost. +\begin{table}\leavevmode\center +\begin{tabular}{|l|l|l|l|}\hline +Segment & 2010 & 2011 & 2012 \\\hline\hline +Communications & 1,867 & 1,946 & 2,096 \\ +High end & 467 & 511 & 550 \\\hline +Consumer & 550 & 592 & 672 \\ +High end & 53 & 62 & 75 \\\hline +Automotive & 243 & 286 & 358 \\ +High end & - & - & - \\\hline +Industrial & 1,102 & 1,228 & 1,406 \\ +High end & 177 & 188 & 207 \\\hline +Military/Aereo & 566 & 636 & 717 \\ +High end & 56 & 65 & 82 \\\hline\hline +Total FPGA/PLD & 4,659 & 5,015 & 5,583 \\ +Total High-End FPGA & 753 & 826 & 914 \\\hline +\end{tabular} +\caption{\label{fga_market} Gartner estimation of worldwide FPGA/PLD consumption (Millions \$)} +\end{table} +\par +Today, several companies (atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp, +Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand +for very high performance (HPC) primes over other requirements. They tend to use the highest +performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative +architectures and algorithms. Companies show up in different "traditional" applications and market +segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC +emulation and prototyping, Mil/aero etc. HPC market size is estimated today by FPGA providers +to 214 M\$. +This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion +of FPGA-based solutions is limited by the flow automation. Nowadays, there are neither commercial +nor free tools covering the whole design process. +For instance, with SOPC Builder from Altera, users can select and parameterize IP components +from an extensive drop-down list of communication, digital signal processor (DSP), microprocessor +and bus interface cores, as well as incorporate their own IP. Designers can then generate +a synthesized netlist, simulation test bench and custom software library that reflect the hardware +configuration. +Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to +simulate the platform at a high design level (system C). +In addition, SOPC Builder is proprietary and only works together with Altera's Quartus compilation +tool to implement designs on Altera devices (Stratix, Arria, Cyclone). +PICO [CITATION] and CATAPULT [CITATION] allow to synthesize coprocessors from a C++ description. +Nevertheless, they can only deal with data dominated applications and they do not handle the +platform level. +The Xilinx System Generator for DSP [http://www.xilinx.com/tools/sysgen.htm] is a plug-in to +Simulink that enables designers to develop high-performance DSP systems for Xilinx FPGAs. +Designers can design and simulate a system using MATLAB and Simulink. The tool will then +automatically generate synthesizable Hardware Description Language (HDL) code mapped to Xilinx +pre-optimized algorithms. +However, this tool targets only DSP based algorithms. +\\ +Consequently, designer developping an embedded system needs to master for example +SoCLib for design exploration, +SOPC Builde at the platform level, +PICO for synthesizing the data dominated coprocessors +and Quartus for design implementation. +This requires an important tools interfacing effort and makes the design process very complex +and achievable only by designers skilled in various domains. +COACH project integrates all these tools in the same framework masking them to the user. +The objective is to allow \textbf{pure software} developpers to realize embedded systems. +\par +The combination of the framework dedicated to software developpers and FPGA target, allows to gain +market share over Multi-core CPUs and GPUs HPC based solutions. +Moreover, one can expect that small and even very small companies will be able to propose embedded +system and accelerating solutions for standard software applications with acceptable prices, thanks + to the elimination of huge hardware investment in opposite to ASIC based solution. +\\ +This new market may explose like it was done by micro-computing in eighties. This success were due +to the low cost of first micro-computers (compared to main frame) and the advent of high level +programming languages that allow a high number of programmers to launch start-ups in software +engineering. + +\subsection{Project position} +\hspace{2cm}\begin{scriptsize}\begin{verbatim} +% 1.2. POSITIONNEMENT DU PROJET +% (2 pages maximum) +% Préciser : +% - positionnement du projet par rapport au contexte développé précédemment : +% vis- à-vis des projets et recherches concurrents, complémentaires ou antérieurs, +% des brevets et standards. +% - positionnement du projet par rapport aux axes thématiques de l'appel à projets. +% - positionnement du projet aux niveaux européen et international. +\end{verbatim} +\end{scriptsize} +The aim of this project is to propose an open-source framework for architecture synthesis +targeting mainly field programmable gate array circuits (FPGA). +\\% LIP6/TIMA +To evaluate the different architectures, the project uses the prototyping platform +of the SoCLIB ANR project (2006-2009). +\\% IRISA +The project will also borrow from the ROMA ANR project (2007-2009) and the ongoing +joint INRIA-STMicro Nano2012 project. In particular we will adapt +existing pattern extraction algorithms and datapath merging techniques to the synthesis of customized +ASIP processors. +\par +%%% 1 -- POUVEZ VOUS CHACUN AJOUTER SVP (SI POSSIBLE) UNE LIGNE +%%% 1 -- REFERANT UN PROJET ANR OU EUROPEEN +%%% 1 -- Projets européens ou ANR réutilisés ou continués +%%% 1 LIP6/TIMA/LAB-STIC OK +Regarding the expertise in High Level Synthesis (HLS), the project leverages on know-how acquired over 15 years +with GAUT project developped in Lab-STIC laboratory and UGH project developped in LIP6 +and TIMA laboratories. \\ +Regarding architecture synthesis skills, the project is based on a know-how acquired over 10 years +with the COSY European project (1998-2000) and the DISYDENT project developped in LIP6. \\ +%%% 1 IRISA OK +Regarding Application Specific Instruction Processor (ASIP) design, the CAIRN group at INRIA Bretagne +Atlantique benefits from several years of expertise in the domain of retargetable compiler (Armor/Calife +since 1996, and the Gecos compilers since 2002). +% LIP FIXME:UN:PEU:LONG ET HORS:SUJET +%CA% The source-level transformations required by the HLS tools will be +%CA% designed in the {\em polyhedral model}, a general framework +%CA% initiated by Paul Feautrier 20 years ago. The programs handled in +%CA% the polyhedral model are such that loop iterators describe a +%CA% polyhedron (hence the name). This includes most of the kernels used +%CA% in embedded applications. This property allows to design precise +%CA% analysis by means of integer programming techniques. +%CA% %communaute active & internationale +%CA% %transfert techno (Reservoir) +%CA% The polyhedral community is very active, and the technological +%CA% transfer has now started. Reservoir Labs inc., a company based in +%CA% New-York, is currently integrating the last polyhedral developments +%CA% in its commercial compiler. +%CA% %transfert techno (gcc) +%CA% Also, polyhedra are progressively migrating into the {\sc GNU Gcc} +%CA% compiler, via {\sc Graphite}, a module initially developed by +%CA% Sebastian Pop. +%CA% %outils existants +%CA% Several tools have been developed in the polyhedral community, +%CA% such as {\sc Piplib} (parameter integer programming library), and +%CA% {\sc Polylib}, a library providing set operations on polyhedra. Both +%CA% tools are almost mandatory in polyhedral tools, and have reached +%CA% a sufficient level of maturity to be considered as standard. +%syntol & bee ??? +% FIN +% and on more than 15 years of experience on parallel hardware generation +% in the polyedral model in the CAIRN group (MMAlpha software +% developped in the group since 1996). +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%% 2 -- A COMPLETER (COURT) +%%% 2 -- For polyedric transformation and memory optimization ... LIP +%%% 2 -- For ASIP IRISA +%%% 2 -- For ... CITI +%%% 2 -- For ... TIMA +\par +The SoCLIB ANR platform were developped by 11 laboratories and 6 companies. It allows to +describe hardware architectures with shared memory space and to deploy software +applications on them to evaluate their performance. +The heart of this platform is a library containing simulation models (in SystemC) +of hardware IP cores such as processors, buses, networks, memories, IO controller. +The platform provides also embedded operating systems and software/hardware +communication components useful to implement applications quickly. +However, the synthesisable description of IPs have to be provided by users. \\ +This project enhances SoCLib by providing synthesisable VHDL of standard IPs. +In addition, HLS tools such as UGH and GAUT allow to get automatically a synthesisable +description of an IP (coprocessor) from a sequential algorithm. +%\par +%%% 2 IRISA ? +%%% 2 ASIP tool such as ... IRISA +%%% 2 ... +%%% 2 Coach uses pattern extractions from ROMA +%\par +%%% 2 LIP ? +\par +The different points proposed in this project cover priorities defined by the commission +experts in the field of Information Technolgies Society (IST) for Embedded +systems: <>. +\\ +Our team aims at covering all the steps of the design flow of architecture synthesis. +Our project overcomes the complexity of using various synthesis tools and description +languages required today to design architectures. + +\section{Scientific and Technical Description} +\subsection{State of the art} +\hspace{2cm}\begin{scriptsize}\begin{verbatim} +% 2. DESCRIPTION SCIENTIFIQUE ET TECHNIQUE +% 2.1. ÉTAT DE L'ART +% (3 pages maximum) +% Décrire le contexte et les enjeux scientifiques dans lequel se situe le projet +% en présentant un état de l'art national et international dressant l'état des +% connaissances sur le sujet. Faire apparaître d'éventuels résultats préliminaires. +% Inclure les références bibliographiques nécessaires en annexe 7.1. +\end{verbatim} +\end{scriptsize} +Our project covers several critical domains in system design in order +to achieve high performance computing. Starting from a high level description we aim +at generating automatically both hardware and software components of the system. + +\subsubsection{High Performance Computing} +Accelerating high-performance computing (HPC) applications with field-programmable +gate arrays (FPGAs) can potentially improve performance. +However, using FPGAs presents significant challenges [1]. +First, the operating frequency of an FPGA is low compared to a high-end microprocessor. +Second, based on Amdahl law, HPC/FPGA application performance is unusually sensitive +to the implementation quality [2]. +Finally, High-performance computing programmers are a highly sophisticated but scarce +resource. Such programmers are expected to readily use new technology but lack the time +to learn a completely new skill such as logic design [3]. +\\ +HPC/FPGA hardware is only now emerging and in early commercial stages, +but these techniques have not yet caught up. +Thus, much effort is required to develop design tools that translate high level +language programs to FPGA configurations. + +\hspace{2cm}\begin{scriptsize}\begin{verbatim} +[1] M.B. Gokhale et al., Promises and Pitfalls of Reconfigurable +Supercomputing, Proc. 2006 Conf. Eng. of Reconfigurable +Systems and Algorithms, CSREA Press, 2006, pp. 11-20; +http://nis-www.lanl.gov/~maya/papers/ersa06_gokhale_paper. +pdf. +[2] D. Buell, Programming Reconfigurable Computers: Language +Lessons Learned, keynote address, Reconfigurable Systems +Summer Institute 2006, 12 July 2006; http://gladiator. +ncsa.uiuc.edu/PDFs/rssi06/presentations/00_Duncan_Buell.pdf +[3] T. Van Court et al., Achieving High Performance +with FPGA-Based Computing, Computer, vol. 40, no. 3, +pp. 50-57, Mar. 2007, doi:10.1109/MC.2007.79 +\end{verbatim} +\end{scriptsize} + +\subsubsection{System Synthesis} +Today, several solutions for system design are proposed and commercialized. The most common are +those provided by Altera and Xilinx to promote their FPGA devices. +\\ +The Xilinx System Generator for DSP [http://www.xilinx.com/tools/sysgen.htm] is a plug-in to +Simulink that enables designers to develop high-performance DSP systems for Xilinx FPGAs. +Designers can design and simulate a system using MATLAB and Simulink. The tool will then +automatically generate synthesizable Hardware Description Language (HDL) code mapped to Xilinx +pre-optimized algorithms. +However, this tool targets only DSP based algorithms, Xilinx FPGAs and cannot handle complete +SoC. Thus, it is not really a system synthesis tool. +\\ +In the opposite, SOPC Builder [CITATION] allows to describe a system, to synthesis it, +to programm it into a target FPGA and to upload a software application. +% FIXME(C2H from Altera, marche vite mais ressource monstrueuse) +Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors. +Users have to provide the synthesizable description with the feasible bus interface. +\\ +In addition, Xilinx System Generator and SOPC are closed world since each one imposes +their own IPs which are not interchangeable. +We can conclude that the existing commercial or free tools does not coverthe whole system +synthesis process in a full automatic way. Moreover, they are bound to a particular device family +and to IPs library. + +\subsubsection{High Level Synthesis} +High Level Synthesis translates a sequential algorithmic description and a constraints set +(area, power, frequency, ...) to a micro-architecture at Register Transfer Level (RTL). +Several academic and commercial tools are today available. +Most common tools are SPARK [HLS1], GAUT [HLS2], UGH [HLS3] in the academic world +and catapultC [HLS4], PICO [HLS5] and Cynthesizer [HLS6] in commercial world. +Despite their maturity, their usage is restrained by: +\begin{itemize} +\item They do not respect accurately the frequency constraint when they target an FPGA device. +Their error is about 10 percent. This is annoying when the generated component is integrated +in a SoC since it will slow down the hole system. +\item These tools take into account only one or few constraints simultaneously while realistic +designs are multi-constrained. +Moreover, low power consumption constraint is mandatory for embedded systems. +However, it is not yet well handled by common synthesis tools. +\item The parallelism is extracted from initial algorithm. To get more parallelism or to reduce +the amout of required memory, the user must re-write it while there is techniques as polyedric +transformations to increase the intrinsec parallelism. +\item Despite they have the same input language (C/C++), they are sensitive to the style in +which the algorithm is written. Consequently, engineering work is required to swap from +a tool to another. +\item The HLS tools are not integrated into an architecture and system exploration tool. +Thus, a designer who needs to accelerate a software part of the system, must adapt it manually +to the HLS input dialect and performs engineering work to exploit the synthesis result +at the system level. +\end{itemize} +Regarding these limitations, it is necessary to create a new tool generation reducing the gap +between the specification of an heterogenous system and its hardware implementation. + +\hspace{2cm}\begin{scriptsize}\begin{verbatim} +[HLS1] SPARK universite de californie San Diego +[HLS2] GAUT UBS/Lab-STIC +[HLS3] UGH +[HLS4] catapultC Mentor +[HLS5] PICO synfora +[HLS6] Cynthesizer Forte design system +\end{verbatim} +\end{scriptsize} + +\subsubsection{Application Specific Instruction Processors} +ASIP (Application-Specific Instruction-Set Processor) are programmable +processors in which both the instruction and the micro architecture have +been tailored to a given application domain (eg. video processing), or +in some extreme cases to a specific application (eg H264 specific ASIP). +This processor specialization usually offers a good compromise between +performance (compared to a pure software implementation on a COTS +embeded processor) and flexibility (compared to an application specific +hardware co-processor). +\\ +As a consequence, this type of architecture is a very attractive choice +as a System on chip building block. In spite of their obvious +advantages, using/designing ASIPs remains a difficult task, since it +involves designing both an efficient micro-architecture and implementing +an efficient compiler for this +specific micro-architecture. +\\ +Recently, the use of instruction set extensions has received a lot of +interest from the embedded systems design community [NIOS2,FSL,ST70], +since it allows to rely on a template micro-architecture in which only a +small fraction of the architecture has to be specialized. Even if such +an approach offers less flexiblity and forbids very tight coupling +between the extensions and the template micro-architecture, it makes the +design of the micro-architecture more tractable and amenable to a fully +automated flow. +\\ +However, to our knowledge, there is still no available open-source +design flow addressing those two design challenges together, either +because the target architecture is proprietary, or because the compiler +technology is closed/commercial. +\\ +In the context of the COACH project, we propose to add to the +infra-structure a design flow targeted to automatic instruction set +extension for the MIPS-based CPU, which will come as a complement or an +alternative to the other proposed approaches (hardware accelerator, +multi processors). + +\subsubsection{Automatic Parallelization} +\begin{Large}\begin{verbatim} +-- A COMPLETER LIP +\end{verbatim} +\end{Large} +%CA% Parallel machines are often difficult and painful to program +%CA% directly, and one would like the compiler to %do the job, that is to +%CA% turn automatically a sequential program into a parallel form. This +%CA% transformation is referred as {\em automatic parallelization}, and has +%CA% been widely addressed since the 70s. Automatic parallelization +%CA% relies on data dependences, which cannot be computed in general.%, as +%CA% %one cannot predict at compile time the variable values on a given +%CA% %execution point. +%CA% This negative result led researchers to (i) find a +%CA% program model in which no approximation is needed (ie polyhedral +%CA% model), (ii) make conservative approximations (iii) remark that +%CA% variable values are known at runtime, and make the decisions during +%CA% program execution. The latter approach is obviously not suitable +%CA% there, as we target hardware generation. We will give there a short +%CA% history of the approaches that fall in the first category. +%CA% +%CA%% In the real world, we deal with a limited amount of processors, +%CA%% and the communication between processors takes time, and is +%CA%% critical for performance. %Whenever we have synchronisation-free +%CA%% parallelism, like for embarrassingly parallel kernels, this is not an +%CA%% issue. But in case of pipelined parallelism, we need to reduce +%CA%% communications as much as possible. +%CA%% So we also need to find parallelism toghether with a proper mapping +%CA%% of operations and data on physical processors. +%CA% +%CA% As programs spend most of there time in loops, the community has +%CA% focused on loop transformations that reveal parallelism. +%CA%%unimodulaire +%CA% The first approaches worked on perfect loop nests, where the tree +%CA% formed by the nested loops is linear. In this program model, the +%CA% loops can be seen as a basis that drive the way the iteration +%CA% domain will be described. Hence, a first idea was to change this +%CA% basis such that one vector (one loop) at least is parallel. To ease +%CA% the code generation, the area of defined by the news vectors must +%CA% be a unit volume. %Otherwise, one would produce an homothetic +%CA%% expansion of the iteration domain, which will force to put modulos +%CA%% in the target code. +%CA% For this reason, these transformations are called {\em unimodular +%CA% transformations}. +%CA%%tiling +%CA% +%CA% The next approaches include {\em loop tiling}, a simple +%CA% partitioning of the iteration domain, whose initial purpose is to +%CA% execute every partition on a different processor. %In the same way, +%CA% The execution order is modified with a proper unimodular +%CA% transformation, then the tiles are obtained by cutting the +%CA% iteration domain with the hyperplanes directed by every vector of +%CA% the new (unimodular) basis, at regular intervals. When the tiling +%CA% hyperplanes are properly chosen, we can both improve data-locality +%CA% on every processor, and reduce the communication between two +%CA% different tiles (which will be mapped on processors). This last +%CA% property implying that one tend to find a degree of parallelism as +%CA% great as possible. +%CA% +%CA%%affine scheduling +%CA% The previous approaches were restricted to kernels with perfect +%CA% loop nests (linear loop tree), and unimodular transformations. The +%CA% last generation of approaches broke with these limitations. We now +%CA% choose a different basis for every assignment, without the +%CA% unimodularity restriction. A dual way to present the things is the +%CA% notion of {\em affine schedule}, introduced by Feautrier [part1], +%CA% that simply assigns an abstract execution date to every assignment +%CA% execution. As an assignment execution is exactly characterised by +%CA% the current value of the loops counters (iteration vector), the +%CA% affine schedule will be defined as an affine form of the iteration +%CA% vector (hence the 'affine'). The affine property allows to use +%CA% integer programming techniques to compute the schedule. With this +%CA% approach, additional techniques are required to allocate the +%CA% parallel operations and the data to processor in an efficient way +%CA% [griebl, feautrier]. +%CA% +%CA%%modularity?? +%CA%%% As loop nests are no longer perfect, we deal with (transformed) +%CA%%% iteration domains of different dimensions, which can possibly (and +%CA%%% certainly) overlap. At this point, a new code generation technique +%CA%%% was needed. The first attempt is due to Chamsky et al. [??], and +%CA%%% was improved by Quillere et al. [QRW]. The code is now implemented +%CA%%% in an efficient tool [cloog], that gave a new life to polyhedral +%CA%%% techniques. +%CA% +%CA%%pluto's tiling +%CA% The tiling techniques were extended to non-perfect loop nest with +%CA% {\em affine partitioning}. Affine partitioning is to affine +%CA% scheduling what (original) tiling was to unimodular +%CA% transformations. An affine partitioning assigns to every assignment +%CA% its coordinates in the basis defined by the normals to the tiling +%CA% hyperplanes. Recently, a way to compute efficient hyperplanes were +%CA% found [uday], with a good data locality, and communications +%CA% confined in a small neighborhood around every processor. +%CA% +%CA%\subsubsection{Source-level Memory Optimisation} +%CA% The HLS process allows to customise memory, which impacts on final +%CA% circuit size and power consumption. Though most HLS tools already +%CA% try to optimise memory usage, it is better to provide an independent +%CA% source-level pass, that could be reused for different tools and in +%CA% other contexts. +%CA% +%CA% There exists many approaches to evaluate and reduce the memory +%CA% requirement of a program. The first approaches are concerned with +%CA% {\em memory size estimation}, which can be defined as the maximum +%CA% number of memory cells used at the same time [clauss,zhao]. These +%CA% approaches provide an estimation as a symbolic expression of program +%CA% parameters, which can be used further to guide loop optimisations. +%CA% However, no explicit way to reduce the memory size is given. {\em +%CA% Intra-array reuse} approaches brake with this limitation, and +%CA% collapse the array cells which are not alive at the same time. The +%CA% collapse is done by means of a data layout transformation, specified +%CA% with a linear (modular) mapping. The first approaches were +%CA% developed at IMEC [balasa,catthoor], and basically try to linearize +%CA% the arrays and fold them using a modulo operator. Then, Lefebvre et +%CA% al. propose a solution to fold independently the array dimensions +%CA% [lefebvre]. Finally, Darte et al. provide a general formalisation of +%CA% the problem, together with a solution that subsumes the previous +%CA% approaches [darte]. A first implementation was made with the tool +%CA% {\sc Bee}, but there are still many limitations. +%CA% +%CA% \begin{itemize} +%CA% \item The tool is restricted to regular programs, whereas more +%CA% general programs could be handled with a conservative array liveness +%CA% analysis. +%CA% +%CA% \item Programs depending on parameters (inputs) are not handled, +%CA% which forbids to handle, for example, the body of tiled loops. +%CA% +%CA% \item The new array layout can brake spatial locality, and then impact +%CA% performance and power consumption. One would like to get a mapping +%CA% that improve or, at least, preserve the spatial locality of the +%CA% program. +%CA% +%CA% \item Finally, the final memory compaction strongly depends on the +%CA% program schedule, and is naturally hindered by the +%CA% parallelism. Consequently, there is a trade-off to find with +%CA% automatic parallelization. An ideal solution would be to reduce +%CA% memory usage, while preserving parallelism. +%CA% \end{itemize} + +\subsubsection{Interfaces} +\begin{Large}\begin{verbatim} +-- A COMPLETER INSA Etat de l'art +\end{verbatim} +\end{Large} +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Objectives and innovation aspects} +\hspace{2cm}\begin{scriptsize}\begin{verbatim} +% 2.2. OBJECTIFS ET CARACTERE AMBITIEUX/NOVATEUR DU PROJET +% (2 pages maximum) +% Décrire les objectifs scientifiques/techniques du projet. +% Présenter l'avancée scientifique attendue. Préciser l'originalité et le caractère +% ambitieux du projet. +% Détailler les verrous scientifiques et techniques à lever par la réalisation du projet. +% Décrire éventuellement le ou les produits finaux développés à l'issue du projet +% montrant le caractère innovant du projet. +% Présenter les résultats escomptés en proposant si possible des critères de réussite +% et d'évaluation adaptés au type de projet, permettant d'évaluer les résultats en +% fin de projet. +% Le cas échéant (programmes exigeant la pluridisciplinarité), démontrer l'articulation +% entre les disciplines scientifiques. +\end{verbatim} +\end{scriptsize} + +% les objectifs scientifiques/techniques du projet. +The objectives of COACH project are to develop a complete framework to +HPC (accelerating solutions for existing software applications) +and embedded applications (implementing an application on a low power standalone device). +The design steps are presented figure 1. +\begin{figure}[hbtp]\leavevmode\center + \includegraphics[width=.8\linewidth]{flow} + \caption{\label{coach-flow} COACH flow.} +\end{figure} +\begin{description} +\item[HPC setup] Here the user splits the application into 2 parts: the host application +which remains on PC and the SoC application which migrates on SoC. +The framework provides a simulation model allowing to evaluate the partitioning. +\item[SoC design] In this phase, +The user can obtain simulators at different abstraction levels of the SoC by giving to COACH framework +a SoC description. +This description consists of a process network corresponding to the SoC application, +an OS, an instance of a generic hardware platform +and a mapping of processes on the platform components. The supported mapping are +software (the process runs on a SoC processor), +XXXpeci (the process runs on a SoC processor enhanced with dedicated instructions), +and hardware (the process runs into a coprocessor generated by HLS and plugged on the SoC bus). +\item[Application compilation] Once SoC description is validated, COACH generates automatically +an FPGA bitstream containing the hardware platform with SoC application software and +an executable containing the host application. The user can launch the application by +loading the bitstream on FPGA and running the executable on PC. +\end{description} + +% l'avancee scientifique attendue. Preciser l'originalite et le caractere +% ambitieux du projet. +The main scientific contribution of the project is to unify various synthesis techniques +(same input and output formats) allowing the user to swap without engineering effort +from one to an other and even to chain them, for example, to run polyedric transformation +before synthesis. +Another advantage of this framework is to provide different abstraction levels from +a single description. +Finally, this description is device family independent and its hardware implementation +is automatically generated. + +% Detailler les verrous scientifiques et techniques a lever par la realisation du projet. +System design is a very complicated task and in this project we try to simplify it +as much as possible. For this purpose we have to deal with the following scientific +and technological barriers. +\begin{itemize} +\item The main problem in HPC is the communication between the PC and the SoC. +This problem has 2 aspects. The first one is the efficiency. The second is to +eliminate enginnering effort to implement it at different abstract levels. +\item COACH design flow has a top-down approach. In the such case, +the required performance of a coprocessor (run frequency, maximum cycles for +a given computation, power consumption, etc) are imposed by the other system +components. The challenge is to allow user to control accurately the synthesis +process. For instance, the run frequency must not be a result of the RTL synthesis +but a strict synthesis constraint. +\item HLS tools are sensitive to the style in which the algorithm is written. +In addition, they are are not integrated into an architecture and system +exploration tool. +Consequently, engineering work is required to swap from a tool to another, +to integrate the resulting simulation model to an architectural exploration tool +and to synthesize the generated RTL description. +%CA Additionnal preprocessing, source-level transformations, are thus +%CA required to improve the process. +%CA Particularly, this includes parallelism exposure and efficient memory mapping. +\item Most HLS tools translate a sequential algorithm into a coprocessor +containing a single data-path and finite state machine (FSM). In this way, +only the fine grained parallelism is exploited (ILP parallelism). +The challenge is to identify the coarse grained parallelism and to generate, +from a sequential algorithm, coprocessor containing multiple communicating +tasks (data-paths and FSMs). +\end{itemize} + +%Presenter les resultats escomptes en proposant si possible des criteres de reussite +%et d'evaluation adaptes au type de projet, permettant d'evaluer les resultats en +%fin de projet. +The main result is the framework. It is composed concretely of: +2 HPC communication shemes with their implementation, +5 HLS tools (control dominated HLS, data dominated HLS, Coarse grained HLS, +Memory optimisation HLS and ASIP), +3 systemC based virtual prototyping environment extended with synthesizable +RTL IP cores (generic, ALTERA/NIOS/AVALON, XILINX/MICROBLAZE/OPB), +one design space exploration tool, +one operating system (OS). +\\ +The framework fonctionality will be demonstrated with XXX-EXAMPLE1, XXX-EXAMPLE2 +and XXX-EXAMPLE3 on 4 archictures (generic/XILINX, generic/ALTERA, +proprietary/XILINX, proprietary/ALTERA). + +%% \section{} +%% %3. PROGRAMME SCIENTIFIQUE ET TECHNIQUE, ORGANISATION DU PROJET +%% \subsection{} +%% %3.1. PROGRAMME SCIENTIFIQUE ET STRUCTURATION DU PROJET +%% %(2 pages maximum) +%% %Présentez le programme scientifique et justifiez la décomposition en tâches du +%% %programme de travail en cohérence avec les objectifs poursuivis. +%% %Utilisez un diagramme pour présenter les liens entre les différentes tâches +%% %(organigramme technique) +%% %Les tâches représentent les grandes phases du projet. Elles sont en nombre limité. +%% %N'oubliez pas les activités et actions correspondant à la dissémination et à la +%% %valorisation. +%% +%% %METTRE UNE FIGURE ICI DECRIVANT LES TACHES ET LEURS INTERACTION (AVEC LE FLOT +%% %EN FILIGRANE ? ) +%% \subsection{} +%% %3.2. MANAGEMENT DU PROJET +%% %(2 pages maximum) +%% %Préciser les aspects organisationnels du projet et les modalités de coordination +%% %(si possible individualisation d'une tâche coordination : cf. tâche 0 du document +%% %de soumission A). +%% \subsection{} +%% %3.3. DESCRIPTION DES TRAVAUX PAR TACHE +%% %(idéalement 1 ou 2 pages par tâche) +%% %Pour chaque tâche, décrire : +%% %- les objectifs de la tâche et éventuels indicateurs de succès, +%% %- le responsable de la tâche et les partenaires impliqués (possibilité de +%% %l'indiquer sous forme graphique), +%% %- le programme détaillé des travaux par tâche, +%% %- les livrables de la tâche, +%% %- les contributions des partenaires (le " qui fait quoi "), +%% %- la description des méthodes et des choix techniques et de la manière dont +%% %les solutions seront apportées, +%% %- les risques de la tâche et les solutions de repli envisagées. + + + + + + Index: r/coach_global.txt =================================================================== --- /anr/coach_global.txt (revision 386) +++ (revision ) @@ -1,142 +1,0 @@ - -The market of digital systems is about 4,600 M\$ today and is estimated to -5,600 M\$ in 2012. However the ever growing applications complexity involves -integration of heterogeneous technologies and requires the design of -complex Multi-Processors System on Chip (MPSoC). - -During the last decade, the design of ASICs (Application Specific -Integrated Circuits) appeared to be more and more reserved to high volume markets, because -the design and fabrication costs of such components exploded, due to increasing NRE (Non -Recurring-Engineering) costs. -Fortunately, FPGA (Field Programmable Gate Array) components, such as the -Virtex5 family from Xilinx or the Stratix4 family from Altera, can nowadays -implement a complete MPSoC with multiple processors and several dedicated -coprocessors for a few Keuros per device. Many applications are initially captured -algorithmically in High-Level Languages (HLLs) such as C/C++. This has led to growing interest -in tools that can provide an implementation path directly from HLLs to hardware. -Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping, -Co-design, High-Level Synthesis...) are now mature and allow the automation of -a system-level design flow. Unfortunately, ESL tool development to date has primarily focused -on the design of hard-wired devices i.e. ASICs and ASSPs (Application Specific Standard Product). -However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design -methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting -designs written in C/C++ language and implementing the function straight into FPGA. -We believe that coupling FPGA technologies and ESL methodologies -will allow both SMEs (Small and Medium Enterprise) and -major companies to design innovative devices and to enter new, low and -medium volume markets. - -The objective of COACH is to provide an integrated design flow, based on the -SoCLib infrastructure~\cite{soclib}, and optimized for the design of -multi-processors digital systems targeting FPGA devices. -Such digital systems are generally integrated -into one or several chips, and there are two types of applications: -They can be embedded (autonomous) applications -such as personal digital assistants (PDA), ambiant computing components, -or wireless sensor networks (WSN). -They can also be extension boards connected to a PC to accelerate a specific computation, -as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP). - -The COACH environment will integrate several hardware and software technologies: - -Design Space Exploration: - The COACH environment will allow to describe an application as a process - network i.e. a set of tasks communicating through FIFO channels. - COACH will allow to map the application on a shared-memory, MPSoC architecture. - It will permit to easily explore the design space to help the system designer - to define the proper hardware/software partitioning of the application. - For each point in the design space, metrics such as throughput, latency, power - consumption, silicon area, memory allocation and data locality will be provided. - These criteria will be evaluated by using the SoCLib virtual prototyping infrastructure - and high-level estimation methodologies. - -Hardware Accelerators Synthesis (HAS): - COACH will allow the automatic generation of hardware accelerators when required. - Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor - (ASIP) design environment and source-level transformation tools (loop transformations - and memory optimisation) will be provided. - This will allow further exploration of the micro-architectural design space. - HLS tools are sensitive to the coding style of the input specification and the domain - they target (control vs. data dominated). - The HLS tools of COACH will support a common language and coding style to avoid - re-engineering by the designer. - -Platform based design: - COACH will handle both Altera and Xilinx FPGA devices. - COACH will define architectural templates that can be customized by adding - dedicated coprocessors and ASIPs and by fixing template parameters such as - the number of embedded processors, the number of sizes of embedded memory banks - or the embedded the operating system. - However, the specification of the application will be independant of both the - architectural template and the target FPGA device. - Basically, the following three architectural templates will be provided: - - A Neutral architectural template based on the SoCLib IP core library and the - VCI/OCP communication infrastructure. - - An Altera architectural template based on the Altera IP core library, the - AVALON system bus and the NIOS processor. - - A Xilinx architectural template based on the Xilinx IP core library, the PLB - system bus and the Microblaze processor. - -Hardware/Software communication middleware: - COACH will implement an homogeneous HW/SW communication infrastructure and - communication APIs (Application Programming Interface), that will be used for - communications between software tasks running on embedded processors and - dedicated hardware coprocessors. - -The COACH design flow will be dedicated to system designers, and will as -much as possible hide the hardware characteristics to the end-user. - -To reach this ambitious goal, the project will rely on the experience and the -complementariness of partners in the following domains: -Operating system and communication middleware (Tima, Lip6), -MPSoC architectures (Tima, Lab-Sticc, Lip6), -ASIP architectures (Inria/Cairn), -High Level Synthesis (Tima, Lab-Sticc, Lip6), and compilation (Ens-Lyon/Lip). - -The COACH project does not start from scratch. -It stronly relies on the SoCLib virtual prototyping platform for prototyping, -(DSX, component library), operating systems (MUTEKH, DNA/OS). -It also leverages on several existing technologies: -on the GAUT and UGH tools for HLS, -on the ROMA project for ASIP, -on the SYNTOL and BEE tools for source-level analysis and transformations -and on the Xilinx and Altera IP core libraries. -Finally it will use the Xilinx and Altera logic and physical synthesis -tools to generate the FPGA configuration bitstreams. - -The COACH proposal has been prepared during one year by a technical working group -involving the 5 academic partners (one monthly meeting from january 2009 to february -2010). The objective was to analyse the issues of integrating -and enhancing the existing tools and tecnnologies into a unique framework. -Most of the general software architecture of the proposed design flow (including the -exchange format specification) has been define by this working group. -Because the COACH project leanes on the ANR SoCLib platform, it may be described as an -extension of the SoCLib platform. - -Two major FPGA companies are involved in the project: Xilinx will contribute -as a contractual partner providing documentation and manpower; Altera will contribute as -a supporter, providing documentation and development boards. These two companies are strongly motivated -to help the COACH project to generate efficient bitsreams for both FPGA families. -The role of the industrial partners \bull, \thales, \navtel and \zied is to provide -real use cases to benchmark the COACH design environment and to analyze the designer productivity -improvements. - -Following the general policy of the SoCLib platform, the COACH project will be an open -infrastructure, available in the framework of the SoCLib server. -The architectural templates, and the COACH software tools will be distributed under the -GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib -IP core library) will be freely available for non commercial use. For industrial exploitation -the technology providers are ready to propose commercial licenses, directly to the end user, -or through a third party. - -Finally, the COACH project is already supported by a large number of PMEs, as demonstrated by the -"letters of interest", that have collected during the preparation of the project : -- ADACSYS -- MDS -- INPIXAL -- CAMKA System -- ATEME -- ALSIM -- SILICOMP-AQL -- ABOUND Logic -- EADS-ASTRIUM Index: r/coach_objectifs.txt =================================================================== --- /anr/coach_objectifs.txt (revision 386) +++ (revision ) @@ -1,30 +1,0 @@ - -Embedded systems (SoC and MPSoC) became an inevitable evolution in the microelectronic industry. Due to the exploding fabrication costs, the ASIC technology (Application Specific Integrated Circuit) is not an option for SMEs (Small and Medium Enterprises). Fortunately, the new FPGA (Field Programmable Gate Array) components, such as the Virtex5 family from \xilinx, or the Stratix4 family from \altera can implement a complete multi-processor architecture on a single device. But the design of embedded system is a long and complex task that requires expertise in software, software/hardware partionning, operating system, hardware design, VHDL/Verilog modeling. Only very few SMEs have these multiple expertises and are present on the embedded system market. - -The major objective of COACH is to provide to SMEs an open-source framework to design embedded systems on FPGA devices. This framework will be dedicated to system-level designer. - -The second objective of COACH is HPC. In HPC (High Performance Computing), the targeted application is running on a PC. The COACH framework will help the system designer to accelerate an HPC applcation by migrating critical parts into a SoC embedded into an FPGA device plugged to the PC PCI/X bus. This will allow SMEs to enter HPC market for applications that cannot be accelerated by he current GPU based solutions. - -To reach these objectives, the key scientific and technical issues are : - -1) Design Space Exploration by Virtual Prototyping - -The COACH environment will allow to easily map a parallel application (described as an abstract process network Model of Computation) on a shared-memory, MPSoC architecture. COACH will permit the system designer to explore the design space, and to define the best hardware/software partitioning of the application. - -2) Integration of system-level modeling and HLS tools - -COACH will support the automated generation of hardware accelerators when required by using High-Level Synthesis (HLS) tools. These HLS tools will be fully integrated into the system-level design environment. Moreover, COACH will support both data and control dominated applications, and the HLS tools of COACH will support a common language and coding style to avoid re-engineering by the designer. - -3) High-level code transformation - -COACH will allow to optimize the memory usage, to enhance the parallelism through loop transformations and parallelization. The challenge is to identify the coarse grained parallelism and to generate, from a sequential algorithm, applications containing multiple communicating tasks. Coach will adapt techniques which were developed in the 1990 for the construction of distributed programs. However, in the context of HLS, there are several original problems to be solved, related to the FIFO communication channels and with memory optimization. COACH will support code transformation by providing a source to source C2C tool. - -4) Unified Hardware/Software communication middleware - -COACH will rely on he SoCLib experience to implement an unified hardware/software communication infrastructure and communication APIs (Application Programming Interface), to support communications between software tasks running on embedded processors and dedicated hardware coprocessors. The main issue here is to support easy migration -from a software implementation to an hardware implementation. - -5) Processor customization - -ASIP (Application Specific Instruction Processor) design will be addressed by the COACH project. COACH will allow system designers to explore the various level of interactions between the original CPU micro-architecture and its extension. It will also allow to retarget the compiler instruction-selection pass. Finally, COACH will integrate ASIP synthesis in a complete System-level design framework. - Index: r/coach_retombees.txt =================================================================== --- /anr/coach_retombees.txt (revision 386) +++ (revision ) @@ -1,15 +1,0 @@ - -Today, FPGAs become important actors in the computational domain that was originally dominated by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed on a per-application basis. For many applications, FPGAs offer significant performance benefits over microprocessors implementation. There is still a performance degradation of one order of magnitude versus an equivalent ASIC implementations, but low cost (500 euros to 10K euros), fast time-to-market and flexibility of FPGAs make them an attractive choice for low-to-medium volume applications. - -Since their introduction in the mid eighties, FPGAs evolved from a simple, low-capacity gate array to devices (Altera STRATIX III, xilinx Virtex V) that provide a mix of coarse-grained data path units, memory blocks, microprocessor cores, on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement complex systems like multi-processors platform with application dedicated coprocessors. This market is in significant expansion and is estimated to 914 M$ in 2012. - -Nowadays, there are no commercial or academic tools covering the whole design flow from the system level specification to the bitstream generation neither for embedded system design nor for HPC. - -The COACH project proposes an open-source framework for mapping multi-tasks software applications on Field Programmable Gate Array circuits (FPGA). It aims to propose solutions to the societal/economical challenges by providing SMEs novel design capabilities enabling them to increase their design productivity with design exploration and synthesis methods that are placed on top of the state-of-the-art methods. - -We believe that the combination of a design environment dedicated to software developpers and FPGA targets, will allow small and even very small companies to propose embedded system and accelerating solutions for standard software applications with attractive and competitive prices. This new market may explode in the same way as the micro-computer market in the eighties, whose success was due to the low cost of the first micro-processors (compared to main frames) and the advent of high level programming languages which allowed a high number of programmers to launch start-ups in software engineering. - -The large number of SMEs that have expressed interest for the COACH project (ten letters of interest collected -in one month) demonstrates that theres is a real need for this type of tools. - -The COACH project can have a strong economical impact. Index: r/coach_summary.txt =================================================================== --- /anr/coach_summary.txt (revision 386) +++ (revision ) @@ -1,36 +1,0 @@ -The objective of COACH is to provide an integrated design flow, based on the SoCLib virtual prototyping infrastructure, and optimized for the design of multi-processors digital systems targeting FPGA devices. Such digital systems are generally integrated into one or several chips, and there are two types of applications: -- They can be embedded (autonomous) applications such as personal digital assistants (PDA), ambiant computing components, or wireless sensor networks (WSN). -- They can also be extension boards connected to a PC to accelerate a specific computation, as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP). - -The COACH project will provide three hardware architectural templates: - - - A Neutral architectural template based on the SoCLib IP core library and the VCI/OCP communication infrastructure. - - An Altera architectural template based on the Altera IP core library, the AVALON system bus and the NIOS processor. - - A Xilinx architectural template based on the Xilinx IP core library, the PLB system bus and the Microblaze processor. - -The COACH design flow will be dedicated to system designers, and will as much as possible hide the hardware characteristics to the end-user. The specification of the application will be independant from the architectural template and the target FPGA device. - -To reach this ambitious goal, the project will rely on the experience and the complementariness of partners in the following domains: -- Operating system and communication middleware (Tima, Lip6) -- MPSoC architectures (Tima, Lab-Sticc, Lip6) -- ASIP architectures (Inria/Cairn) -- High Level Synthesis (Tima, Lab-Sticc, Lip6), and compilation (Ens-Lyon/Lip) - -The COACH project does not start from scratch. It stronly relies on the SoCLib virtual prototyping platform for prototyping, (DSX, component library), operating systems (MUTEKH, DNA/OS). It also leverages on several existing technologies: the GAUT and UGH tools for HLS, the ROMA project for ASIP, the SYNTOL and BEE tools for source-level analysis and transformations, and the Xilinx and Altera IP core libraries. Finally it will use the Xilinx and Altera logic and physical synthesis tools to generate the FPGA configuration bitstreams. - -Two major FPGA companies are involved in the project: Xilinx will contribute as a contractual partner providing documentation and manpower; Altera will contribute as a supporter, providing documentation and development boards. These two companies are strongly motivated to help the COACH project to generate efficient bitsreams for both FPGA families. - -The role of the industrial partners Bull, Thales, Navtel and Flexras is to provide real use cases to benchmark the COACH design environment and to evaluate the designer productivity improvements. - -Following the general policy of the SoCLib platform, the COACH project will be an open infrastructure, available in the framework of the SoCLib server. The architectural templates, and the COACH software tools will be distributed under the GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib IP core library) will be freely available for non commercial use. For industrial exploitation the technology providers are ready to propose commercial licenses, directly to the end user, or through a third party. - -Finally, the COACH project is already supported by a large number of PMEs, as demonstrated by the "letters of interest", that have collected during the preparation of the project : - - ADACSYS - - MDS - - INPIXAL - - CAMKA System - - ATEME - - ALSIM - - SILICOMP-AQL - - ABOUND Logic - - EADS-ASTRIUM Index: r/coach_summary_fr.txt =================================================================== --- /anr/coach_summary_fr.txt (revision 386) +++ (revision ) @@ -1,39 +1,0 @@ -L'objectif du projet COACH est de fournir un environnement complet de conception de systèmes numériques multi-processeurs qui cible les circuits FPGA. Cet environnement sera basé sur la plate-forme SocLib de prototypage virtuel. Ces systèmes numériques sont en général intégrés dans un ou plusieurs circuits et il y a principalement deux types d'applications: - - des applications autonomes comme celles embarquées dans des PDA, des composants domotiques ou des réseaux de capteurs; - - des cartes d'extension connectées à un PC pour du calcul haute performance (HPC) ou du traitement de signal haute performance (HSSP). - -Le projet COACH fournira trois patrons architecturaux. - - Le patron architectural neutre qui sera basé sur la bibliothèque d'IP cores de - SocLib et sur l'infrastructure de communication VCI/OCP. - VCI/OCP communication infrastructure. - - Le patron architectural Altera qui sera basé sur la bibliothèque d'IP cores d'Altera, - le bus AVALON et le processeur NIOS. - - Le patron architectural Xilinx qui sera basé sur la bibliothèque d'IP cores de Xilinx, - le bus PLB et le processeur Microblaze. - -L'environnement de conception COACH sera conçu pour être utilisable pas un concepteur système. Pour cela il masquera aux utilisateurs les caractéristiques matérielles fines. De plus les descriptions des applications seront totalement indépendante des patrons architecturaux ainsi que du circuit FPGA visé. - -Pour atteindre ces objectifs ambitieux, le projet repose sur la complémentarité et l'expérience des partenaires dans les domaines suivants: - - système d'exploitation et middleware de communication (Tima, Lip6), - - architectures MPSoC (Tima, Lab-Sticc, Lip6), - - architectures ASIP (Inria/Cairn), - - synthèse de haut niveau (Tima, Lab-Sticc, Lip6), et compilation (Ens-Lyon/Lip). - -Le projet COACH ne démarre pas de rien mais s'appuie fortement sur la plate-forme SocLib (DSX, bibliothèque de composants), sur les systèmes d'exploitation (MUTEKH, DNA/OS). Il tirera également profit de plusieurs outils existants: les outils UGH et GAUT pour la synthèse de haut niveau, le projet ROMA pour les processeurs à instructions spécifiques (ASIP), les outils SYNTOL et BEE pour les transformations et l'analyse au niveau source, les bibliothèques de composants d'Altera et Xilinx. Enfin il utilisera les outils de synthèse logique et physique d'Altera et de Xilinx pour générer les bitstreams de configuration des FPGA. - -Les deux plus grandes sociétés du domaine des FPGA sont impliquées dans le projet. Xilinx est partenaire du projet. Altera contribue au projet en fournissant au projet de la documentation et des cartes de développement. Ces deux sociétés sont très motivées à aider ce projet pour générer des bitstreams optimisés pour leurs circuits FPGA. - -Le rôle des partenaires industriels Bull, Thales, Navtel and Flexras est de fournir des applications industrielles pour évaluer les performances de l'environnement COACH ainsi que mesurer les gains de productivité obtenus. - -Conformément à la politique générale de la plate-forme SocLib, le projet COACH sera sous licence libre, et disponible sur le serveur de la plate-forme SocLib. Les patrons architecturaux et les logiciels seront distribués sous la licence GPL, les modèles en VHDL synthétisable des composants du patron architectural neutre seront distribués aussi librement mais leur utilisation sera restreinte à un usage non commercial. Pour une utilisation commerciale de ces composants, les concepteurs de ces modèles fourniront des licences commerciales soit directement à l'utilisateur final soit à une tierce partie. - -Finalement, le projet COACH est soutenu par un grand nombre de PME comme le montrent les lettres d'intérêt qui ont été collectées: - - ADACSYS - - MDS - - INPIXAL - - CAMKA System - - ATEME - - ALSIM - - SILICOMP-AQL - - ABOUND Logic - - EADS-ASTRIUM Index: r/coach_tasks.txt =================================================================== --- /anr/coach_tasks.txt (revision 386) +++ (revision ) @@ -1,38 +1,0 @@ - - -The project is split into 8 tasks described in short below: - -T1) Project management - -This task relates to the monitoring of the COACH project. It includes a monthy meeting of the steering committee. - -T2) Backbone - -This task tackles the fundamental points of the project that are the defintion of the COACH inputs and outputs, the inter-tools exchange formats, the three supported architectural templates, the hardware/software communication middleware, and the general design flow. This task contains also the development of the associated tools. - -T3) System generation - -This task addresses the virtual prototyping and the generation of the final bitstream (including hardware and -embedded software). - -T4) Hardware accelerator synthesis front-end - -This task mainly focusses on four functionalities: optimization of the memory usage, parallelism enhancement through loop transformations, coarse grain parallelization and ASIP generation. - -T5) Hardware accelerator synthesis back-end - -This task groups two functionalities: High-Level Synthesis of data dominated coprocessors and High Level Synthesis of control dominated coprocessors. It contains also the development of a a generic retiming mechanism -to adapt the coprocessors to the system frequency. - -T6) PC/FPGA communication middleware - -This task is mainly dedicated to HPC. Subtasks are mainly the partitioning evaluation tool, the software drivers for both PC and FPGA-SoC sides, the hardware communication components and the support for dynamic partial reconfiguration. - -T7) Industrial demonstrators - -This task groups the demonstrators of the COACH project. Most subtasks are industrial applications that will be used to evaluate the COACH framework. Another subtask is to evaluate the interfacing between the COACH framework and a proprietary system-level design tool (Thales). A third subtask is to evaluate the COACH framework on a third embedded FPGA architecture (Flexras). - -T8) Dissemination - -This task is related to the dissemination of the project results. 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-#define PICT_TOPSEP 0.0 -#define PICT_BOTSEP 3.0 -#define PICT_LEFTSEP 2.0 -#define PICT_RIGHTSEP 3.0 -#define PICT_VSEP 2.0 -#define PICT_HSEP 2.0 - -#define PICT_MONTHHEIGHT 5 // police height -#define PICT_MONTHWIDTH (10./3.) - -#define TASK_VSEP 2 -#define TASK_BGC0 "gtcTaskBG0" -#define TASK_BGC1 "gtcTaskBG1" -#define TASK_TITLEHEIGHT 6. -#define TASK_TITLEFONTHEIGHT 2. - -#define DELIVRABLE_VSEP 1 -#define DELIVRABLE_HEIGHT 3 -#define DELIVRABLE_LABELWIDTH 7.5 -#define DELIVRABLE_LABELHEIGHT DELIVRABLE_HEIGHT -#define DELIVRABLE_TITLEWIDTH 38 -#define DELIVRABLE_TITLEHEIGHT DELIVRABLE_HEIGHT -#define DELIVRABLE_BOXHEIGHT (DELIVRABLE_HEIGHT) - -char* task_names[] = { - 0, - "Project management", - "Backbone infrastructure", - "System generation", - "HAS front-end", - "HAS back-end", - "PC/FPGA communication middleware", - "Industrial demonstrators", - "Dissemination", - 0 -}; -char* subtask_names[20][20]; -char* get_subtask_name(int tn, int stn) -{ - char* ret=subtask_names[tn][stn]; - if (ret==0) { - fprintf(stderr,"ERROR: no name found for st%d-%d sub-task.\n",tn,stn); - return ""; - } else - return ret; -} - -struct partner_def { char *key, *name, *fnfull, *fnshort; } partner_table[] = { - { "UNKNOW" ,"relax" ,0 ,0 }, - { "mds" ,"mds" ,"table_mds_full.tex" ,"table_mds_short.tex" }, - { "upmc" ,"upmc" ,"table_upmc_full.tex" ,"table_upmc_short.tex" }, - { "ubs" ,"ubs" ,"table_ubs_full.tex" ,"table_ubs_short.tex" }, - { "lip" ,"lip" ,"table_inria_compsys_full.tex","table_inria_compsys_short.tex" }, - { "tima" ,"tima" ,"table_tima_full.tex" ,"table_tima_short.tex" }, - { "inria" ,"inria" ,"table_inria_cairn_full.tex" ,"table_inria_cairn_short.tex" }, - { "bull" ,"bull" ,"table_bull_full.tex" ,"table_bull_short.tex" }, - { "thales" ,"thales" ,"table_thales_full.tex" ,"table_thales_short.tex" }, - { 0 ,0 ,0 ,0 }, -}; - -typedef struct _Tlivrable { - char v; // 0, 1, 2, ..., F - char* kind; - char* title; - int bm,em; // mois de bebut et de fin - double hman[3]; // nombre de mh par an - int tn,stn,dn,vn; // task, sub-task, number - int leader; // 1: the partner leads this livrable - // 0: the partner helps for this livrable - int partner; // index dans partner_table - // these fields are filled by the program for data[tn][0][0][0] - double task_y; // top of task - double task_dy; // bot of task is task_y+task_dy - double task_y_del; // delivrables start at task_y+task_y_del - double nbma[3]; // durée en mois par annee - // these fields are filled by the program for data[tn][stn][dn][0] - struct _Tlivrable // versions of the livrable - **vers; // null termiated (vers[i] = data[tn][stn][dn][j]) - // this->leader == 1 - // vers[0] = this - // vers[i]->leadaer == this->leader - // vers[i]->partner == this->partner - int nbvers; // nombre de vers - double height; // height of livrable - // int del_bm,del_em; // mois de bebut et de fin cummule - // these fields are filled by the program for all elements - int nbTitleLines; - char* titleLines[5]; // null termiated - struct _Tlivrable // participant to the livrable - **part; // null termiated (vers[i] = data[tn][stn][dn][j]) - // this->leader == 1 - // vers[i] != this - // vers[i]->leader == 0 - // vers[i]->partner != this->partner - int nbpart; // nombre de vers -} Tlivrable; - -#define T_MAX 10 -#define S_MAX 10 -#define D_MAX 10 -#define V_MAX 10 -typedef struct _Tdata { - FILE* os; - Tlivrable* ls[T_MAX][S_MAX][D_MAX][V_MAX]; -} Tdata; -Tdata data_org; -Tdata* curr; - -Tdata* data_new(int *tnplus, int *tnmoins) -{ - int i,skip; - int tn,stn,dn,v; - Tdata* data = malloc(sizeof(*data)); - memset(data,0,sizeof(*data)); - for (tn=0 ; tntn ) { - skip=0; - break; - } } } - if (skip) continue; - // tnmoins treatment - skip = 0; - if (tnmoins!=0) { - for (i=0 ; tnmoins[i]!=-1 ; i++) { -//fprintf(stderr,"i=%d data_org.ls[tn][stn][dn][v]->tn=%d tnmoins[i]=%d\n",i,data_org.ls[tn][stn][dn][v]->tn,tnmoins[i]); - if ( tnmoins[i]==data_org.ls[tn][stn][dn][v]->tn ) { - skip=1; - break; - } } } -//fprintf(stderr,"selected: [tn][stn][dn][v]=%d,%d,%d,%d skip=%d\n",tn,stn,dn,v,skip); - if (skip) continue; - Tlivrable* l=malloc(sizeof(*l)); - *l = *data_org.ls[tn][stn][dn][v]; - data->ls[tn][stn][dn][v] = l; -//fprintf(stderr,"selected: [tn][stn][dn][v]=%d,%d,%d,%d\n",tn,stn,dn,v); - } - return data; -} - -int milestones[100]; - -char* gen_label_base(char* buf,Tlivrable*p) - { if (p->dn >=0) sprintf(buf,"D%d%d%d",p->tn,p->stn,p->dn); else sprintf(buf,""); return buf; } -char* gen_label_vers(char* buf,Tlivrable*p) - { if (p->nbvers<=1) strcpy(buf,""); else sprintf(buf,"V%c",p->v); return buf; } -char* gen_label_full(char* buf,Tlivrable*p) - { char b[100],v[100]; gen_label_base(b,p); gen_label_vers(v,p); - sprintf(buf,"%s%s%s",b,*v?"-":"",v); return buf; } - -void print_put(double x,double y, const char* object) - { fprintf(curr->os,"\\put(%.2f,%.2f){%s}\n",x,y,object); } -void print_hline(double x,double y, double len, const char* color) -{ - char object[1024]; - if (color!=0) { fprintf(curr->os,"\\bgroup\\color{%s}\n",color); } - sprintf(object,"\\line(1,0){%.2f}",len); - print_put(x,y,object); - if (color!=0) { fprintf(curr->os,"\\egroup\n"); } -} -void print_vline(double x,double y, double len, const char* color) -{ - char object[1024]; - if (color!=0) { fprintf(curr->os,"\\bgroup\\color{%s}\n",color); } - sprintf(object,"\\line(0,1){%.2f}",len); - print_put(x,y,object); - if (color!=0) { fprintf(curr->os,"\\egroup\n"); } -} -void print_box( - int filled, char* vers, // vers may be 0, - double x,double y, double dx, double dy, - const char* boxcolor, // may be 0 (default COLOR_BOX_HEAVY) - const char* bgcolor, // may be 0 (not set) - const char* textcolor // may be 0 (black) -){ - double tn=.4; - char object[1024]; - if ( boxcolor==0 ) boxcolor = COLOR_BOX_HEAVY; - if ( filled==1 ) { - sprintf(object, - "\\fcolorbox{black}{%s}{\\makebox(%.2f,%.2f){}}", - boxcolor,dx-2-tn,dy-2-tn); - print_put(x,y+1,object); - } else { - double tn2=tn/2; - double e=.1; - fprintf(curr->os,"\\bgroup\\color{%s}\n",boxcolor); - fprintf(curr->os,"\\linethickness{%.2fmm}\n",tn); - print_hline(x+tn2-e ,y, dx ,0); - print_hline(x+tn2-e ,y+dy, dx ,0); - print_vline(x+tn-e ,y+e, dy-2*e ,0); - print_vline(x+dx-2*e,y+e, dy-2*e ,0); - fprintf(curr->os,"\\egroup\n"); - } - if (vers) { - sprintf(object,"\\begin{tiny}\\textbf{%s}\\end{tiny}",vers); - print_put(x+1,y+.5,object); - } -} - -void gen_titleLines(Tlivrable*p) -{ - const char* macro="\\ganttlf"; - char* pc = p->title; - char* pc2; - - if (pc==0) return; - - while ( (pc2=strstr(pc,macro))!=0 ) { - char c = *pc2; - *pc2 = 0; - p->titleLines[p->nbTitleLines]=strdup(pc); - p->nbTitleLines+=1; - *pc2=c; - pc=pc2+strlen(macro); - } - p->titleLines[p->nbTitleLines]=strdup(pc); - p->nbTitleLines+=1; -} -%} - -%option noyywrap - -%% - int tn,stn,dn,v,bm,em; char* title; char* kind; - double an[3]; - char* an_comment; - int leader; - int partner; -#.*\n ; -L=1 { leader=1; } -L=0 { leader=0; } -T=[0-9]+ { tn=atoi(yytext+2); } -S=[0-9]+ { stn=atoi(yytext+2); } -D=[0-9]+ { dn=atoi(yytext+2); } -V=V[1-8F] { v=yytext[3]; } -ML=[0-9]+ { - int i; - for (i=0 ; milestones[i]!=0 ; i++); - milestones[i] = atoi(yytext+3); - } -STN=.* { - int nb,tn, stn; - char tmp[1000]; - nb=sscanf(yytext+4,"%d%d%s",&tn,&stn,tmp); - if ( nb==3 && 0<=tn && tn<10 && 0<=stn && stn<10 ) { - char* p =strstr(yytext+4,tmp); - subtask_names[tn][stn]=strdup(p); - } else { - fprintf(stderr, "bad formated ST rule (ignored): %s.\n",yytext); - } -} -BM=[0-9]+ { bm=atoi(yytext+3); } -EM=[0-9]+ { em=atoi(yytext+3); } -R=none { an[0]=0; an[1]=0; an[2]=0; an_comment=0; } -R=[0-9:.]+ { - char tmp[1000]; - int status = sscanf(yytext+2,"%lf:%lf:%lf:%s",an+0,an+1,an+2,tmp); - if (status<3) { - fprintf(stderr, - "%s: is not resource definition, expected format \"N:N:N\" (near D%d%d%d-V%c)\n", - yytext+2,tn,stn,dn,v); - an[0]=0; an[1]=0; an[2]=0; an_comment=0; - } else if (status==3) { - an_comment = 0; - } else - an_comment = strdup(tmp); - } -PART="{"[^}]+"}" { - int i; - partner=-1; - for (i=0; partner_table[i].key!=0 ; i++) { - if (strstr(yytext,partner_table[i].key)!=0 ) { - partner=i; - break; - } - } - if ( partner==-1 ) { - fprintf(stderr,"%s: does not contains a partner key (near D%d%d%d-V%c)\n", - yytext+5,tn,stn,dn,v); - partner=0; - } - } -KIND="{"[^}]+"}" { - yytext[yyleng-1]=0; - kind= strdup(yytext+6); - if ( strcmp(kind,"x")!=0 && strcmp(kind,"d")!=0 && strcmp(kind,"h")!=0 && - strcmp(kind,"d+x")!=0 ) - fprintf(stderr,"ERROR:D%d%d%d invalid KIND: %s\n",tn,stn,dn,kind); - } -KIND="{}" { - yytext[yyleng-1]=0; - kind= strdup(yytext+6); - } -TITLE=.*\n { - char* pc=yytext+6; - yytext[yyleng-1]=0; - while ( *pc==' ' || *pc=='\t' ) pc+=1; - title=strdup(pc); - Tlivrable* p= (Tlivrable*) calloc(sizeof(*p),1); - p->tn = tn; - p->stn = stn; - p->dn = dn; - p->v = v; - p->hman[0] = an[0]; - p->hman[1] = an[1]; - p->hman[2] = an[2]; - p->leader = leader; - p->partner = partner; - p->title = title; - p->bm = bm; - p->em = em; - p->kind = kind; - gen_titleLines(p); - - for (v=0; data_org.ls[tn][stn][dn][v]!=0 ; v++); - data_org.ls[tn][stn][dn][v] = p; -//fprintf(stderr,"ADDED: %d %d %d %d\n",tn,stn,dn,v); - tn=stn=dn=v=bm=em=0; - title=kind=0; - an[0]= an[1]=an[1]=0; - an_comment=0; - partner=0; - leader=0; - } -[ \t\n] ; -. { fprintf(stderr,"%c: unexpected value in anr.gantt file (near D%d%d%d-V%c)\n", - *yytext,tn,stn,dn,v); } -%% - -void prepare0(Tdata* data) -{ -int tn,stn,v; -int i0,i1,i; - for (tn=0 ; tnls[tn][stn][i][0]); fprintf(stderr,"\n"); - while (1) { - for (i0=0 ; i0ls[tn][stn][i0][0] == 0) break; - for (i1=i0+1 ; i1ls[tn][stn][i1][0] != 0) break; - if (i1>=D_MAX) break; - // shift - for (i=0 ; (i1+i)ls[tn][stn][i0+i][v] = data->ls[tn][stn][i1+i][v]; - data->ls[tn][stn][i1+i][v] = 0; - } - } -//fprintf(stderr,"AVANT:t=%d:%d:: ",tn,stn); for (i=0; ils[tn][stn][i][0]); fprintf(stderr,"\n"); - } -} -void prepare1(Tdata* data) -{ -int tn,dn,v; -int i0,i1,i; - for (tn=0 ; tnls[tn][i][0][0]); fprintf(stderr,"\n"); - while (1) { - for (i0=0 ; i0ls[tn][i0][0][0] == 0) break; - for (i1=i0+1 ; i1ls[tn][i1][0][0] != 0) break; -//fprintf(stderr,"%d %d %d\n",tn,i0,i1); - if (i1>=S_MAX) break; - // shift - for (i=0 ; (i1+i)ls[tn][i0+i][dn][v] = data->ls[tn][i1+i][dn][v]; - data->ls[tn][i1+i][dn][v] = 0; - } - } -//fprintf(stderr,"APRES:t=%d:: ",tn,i0,i1); for (i=0; ils[tn][i][0][0]); fprintf(stderr,"\n"); - } -} -void prepare2(Tdata* data) -{ -int tn0,tn1,stn,dn,vn; -int moved=1; - while (moved) { - moved=0; - for (tn0=0 ; tn0ls[tn0][0][0][0] == 0) break; - for (tn1=tn0+1 ; tn1ls[tn1][0][0][0] != 0) break; - if (tn1==T_MAX) break; - for (stn=0 ; stnls[tn0][stn][dn][vn] = data->ls[tn1][stn][dn][vn]; - data->ls[tn1][stn][dn][vn] = 0; - } - moved=1; - } -} - -void prepare3(Tdata* data) -{ -int tn,stn,dn,vn,cnt; -Tlivrable* tmp; - for (tn=0 ; tnls[tn][stn][dn][0]; - if (p==0) continue; - p->nbvers=0 ; - p->nbpart=0 ; - for (vn=0 ; vnls[tn][stn][dn][vn]; - if (tmp==0) continue; - if (tmp->leader==0) - p->nbpart+=1; - else - p->nbvers+=1; - } - p->vers=(Tlivrable**)malloc(sizeof(*p->vers)*(p->nbvers+1)); - for (vn=0,cnt=0 ; vnls[tn][stn][dn][vn]; - if (tmp!=0 && tmp->leader==1) { - p->vers[cnt++] = tmp; - tmp->nbvers = p->nbvers; - } - } - p->vers[cnt] = 0; - if (p->nbpart!=0) { - p->part=(Tlivrable**)malloc(sizeof(*p->part)*(p->nbpart+1)); - for (vn=0,cnt=0 ; vnls[tn][stn][dn][vn]; - if (tmp!=0 && tmp->leader==0) { - p->part[cnt++] = tmp; - } - } - p->part[cnt] = 0; - } - - p->height = 1.0*DELIVRABLE_HEIGHT; - if (p->nbTitleLines>=1) { - double h=0; - h += p->vers[p->nbvers-1]->nbTitleLines*DELIVRABLE_TITLEHEIGHT; - h += (p->vers[p->nbvers-1]->nbTitleLines-1)*(DELIVRABLE_TITLEHEIGHT/5.); - if ( h>p->height) p->height=h; - } - Tlivrable* lu= p->vers[p->nbvers-1]; - int i; -//fprintf(stderr,"--------------------\n"); - for (i=0 ; inbvers ; i++) { - Tlivrable* l= p->vers[i]; - double bm= l->bm; - double em= l->em; -//fprintf(stderr," %d%d%d-V%c: bm=%2.f em=%2.f --> %2.1f %2.1f %2.1f\n",l->tn,l->stn,l->dn,l->v,bm,em, lu->nbma[0],lu->nbma[1],lu->nbma[2]); - if (bm<12 && em>0) { - lu->nbma[0] += (em>12?12:em)-bm; - bm=12; - } - if (bm<24 && em>12) { - lu->nbma[1] += (em>24?24:em)-bm; - bm=24; - } - if (bm<36 && em>24) { - lu->nbma[2] += em-bm; - } -//fprintf(stderr," %d%d%d-V%c: bm=%2.f em=%2.f --> %2.1f %2.1f %2.1f %p\n",l->tn,l->stn,l->dn,l->v,bm,em, lu->nbma[0],lu->nbma[1],lu->nbma[2], lu); - } - } -} - -double task_livrable_height(int tn, double* delivrable_y) -{ -int stn,dn,nblivrables=0; -double height=0; - height += TASK_TITLEHEIGHT ; - *delivrable_y = height; - for (stn=0 ; curr->ls[tn][stn][0][0]!=0 ; stn++) - for (dn=0 ; curr->ls[tn][stn][dn][0]!=0 ; dn++) { - if ( curr->ls[tn][stn][dn][0]->leader==0 ) continue; - nblivrables += 1; - height+=curr->ls[tn][stn][dn][0]->height; - } - height += DELIVRABLE_VSEP/2; - height += (nblivrables-1)*DELIVRABLE_VSEP; - height += DELIVRABLE_VSEP/2; - return height; -} - -void task_box(double pictwidth) -{ - int tn; - for ( tn=0 ; curr->ls[tn][0][0][0]!=0 ; tn++ ) { - const char* color= (tn%2)!=0 ? TASK_BGC1 : TASK_BGC0 ; - fprintf(curr->os, - "\\put(%.2f,%.2f){\\fcolorbox{black}{%s}{\\makebox(%5.2f,%5.2f){}}}\n", - 0.0,curr->ls[tn][0][0][0]->task_y, - color, - pictwidth,curr->ls[tn][0][0][0]->task_dy - ); - } -} - -void month_grid(double x, double y, double dx, double dy) -{ - int i; - for (i=0 ; i<=36 ; i+=1,x+=PICT_MONTHWIDTH) { - if ( (i%3)!=0 ) continue; - fprintf(curr->os, - "\\put(%5.1f,%5.1f){\\line(0,1){%5.1f}}\\put(%5.1f,%5.1f){%d}\n", - x,y,dy-PICT_MONTHWIDTH-PICT_VSEP, - x-2,y+dy-PICT_MONTHHEIGHT, - i - ); - } -} - -void print_milestones(double x, double y, double dx, double dy) -{ - int i; - double tn=.3; - //x=x-tn/2; - fprintf(curr->os,"\\bgroup\n"); - fprintf(curr->os,"\\color{red}\n"); - fprintf(curr->os,"\\linethickness{%.2fmm}\n",tn); - for (i=0 ; milestones[i]!=0 ; i+=1) { - double xx= x + milestones[i]*PICT_MONTHWIDTH; - print_vline(xx,y,dy-PICT_MONTHWIDTH-PICT_VSEP,0); - char tmp[100]; - sprintf(tmp,"M%d",i+1); - print_put(xx-2,y-3,tmp); - } - fprintf(curr->os,"\\egroup\n"); -} - -double delivrable( - double label_x, double box_x, double title_x, - double y, - int tn, int stn, int dn) -{ - Tlivrable* top=curr->ls[tn][stn][dn][0]; - Tlivrable* last=curr->ls[tn][stn][dn][top->nbvers-1]; - char tmp[1000],label[1000],title[1000]; - double y0; - int v; - double label_dx = DELIVRABLE_LABELWIDTH ; - double label_dy = DELIVRABLE_LABELHEIGHT ; - double boxx,box_dx; - double box_dy = DELIVRABLE_BOXHEIGHT ; - double title_dx = DELIVRABLE_TITLEWIDTH ; - double title_dy = DELIVRABLE_TITLEHEIGHT ; - -//print_hline(0,y,180,0); - gen_label_base(label,top); - // y -= DELIVRABLE_HEIGHT; - y -= top->height ; -//print_hline(0,y,180,0); - fprintf(curr->os,"%% Delivrable %s (tn=%d stn=%d dn=%d\n",label,tn,stn,dn); - - // print label - //y0 = (DELIVRABLE_HEIGHT-DELIVRABLE_LABELHEIGHT)/2; - y0 = (top->height-DELIVRABLE_LABELHEIGHT)/2; - sprintf(tmp,"\\ganttlabelstyle{%s}",label); - print_put(label_x,y+y0,tmp); - // print title - if (last->nbTitleLines==1) { - y0 = (DELIVRABLE_HEIGHT-DELIVRABLE_TITLEHEIGHT)/2; - y0 += DELIVRABLE_TITLEHEIGHT/5. ; - sprintf(tmp,"\\gantttitlestyle{%s}",last->title); - print_put(title_x,y+y0,tmp); - } else if (last->nbTitleLines>1) { - int i; - // y0 = (DELIVRABLE_HEIGHT-DELIVRABLE_TITLEHEIGHT)/2; - y0=DELIVRABLE_TITLEHEIGHT/5.; - sprintf(tmp,"\\gantttitlestyle{\\shortstack[l]{%s",last->titleLines[0]); - for (i=1 ; inbTitleLines ; i+=1) { - strcat(tmp,"\\\\"); - strcat(tmp,last->titleLines[i]); - } - strcat(tmp,"}}"); - print_put(title_x,y+y0,tmp); - } - - // print box - //y0 = (DELIVRABLE_HEIGHT-DELIVRABLE_BOXHEIGHT)/2; - y0 = (top->height-DELIVRABLE_BOXHEIGHT)/2; - if ( last==top ) { - Tlivrable* l=top; - boxx = box_x + l->bm*PICT_MONTHWIDTH ; - box_dx = (l->em - l->bm) * PICT_MONTHWIDTH; - print_box(1,0,boxx,y+y0,box_dx,box_dy,COLOR_BOX_LIGHT,0,0); - print_box(0,0,boxx,y+y0,box_dx,box_dy,0,0,0); - } else for (v=0 ; vnbvers ; v+=1) { - Tlivrable* l=curr->ls[tn][stn][dn][v] ; - gen_label_vers(tmp,l); - boxx = box_x + l->bm*PICT_MONTHWIDTH ; - box_dx = (l->em - l->bm) * PICT_MONTHWIDTH; - print_box(1,0,boxx,y+y0,box_dx,box_dy,COLOR_BOX_LIGHT,0,0); - print_box(0,tmp,boxx,y+y0,box_dx,box_dy,0,0,0); - } - y -= DELIVRABLE_VSEP; - return y; -} - -void task_delivrable(double label_x, double box_x, double title_x, int tn) -{ -int stn,dn; -Tlivrable* task=curr->ls[tn][0][0][0]; -double y = task->task_y+task->task_dy-task->task_y_del; - char tmp[1000]; - sprintf(tmp,"\\textbf{Task-%d \\textit{%s}}",task->tn,task_names[task->tn]); - print_put(label_x/2,y+(TASK_TITLEHEIGHT-TASK_TITLEFONTHEIGHT)/2,tmp); - - //y += DELIVRABLE_VSEP/2. ; - for (stn=0 ; curr->ls[tn][stn][0][0]!=0 ; stn++) - for (dn=0 ; curr->ls[tn][stn][dn][0]!=0 ; dn++) { - if (curr->ls[tn][stn][dn][0]->dn >=0) - y=delivrable(label_x,box_x,title_x,y,tn,stn,dn); - } -} - -void do_gantt(const char* fn, int* tnplus, int* tnmoins) -{ - int tn; - double pictwidth, pictheight; - double gantt_x,gantt_y; - double gantt_dx,gantt_dy; - - double label_x,title_x; - curr = data_new(tnplus,tnmoins); - if ( (curr->os=fopen(fn,"w"))==0 ) { - fprintf(stderr,"can not open %s file for writing.\n",fn); - fprintf(stderr,"generation of %s graph is skipped.\n",fn); - return; - } - prepare0(curr); - prepare1(curr); - prepare2(curr); - prepare3(curr); - - pictheight=0 ; - pictheight += PICT_BOTSEP ; - for ( tn=0 ; curr->ls[tn][0][0][0]!=0 ; tn++ ); - for ( tn=tn-1 ; tn>=0 ; tn-- ) { - double offset; - curr->ls[tn][0][0][0]->task_y = pictheight; - curr->ls[tn][0][0][0]->task_dy = task_livrable_height(tn,&offset); - curr->ls[tn][0][0][0]->task_y_del = offset; - pictheight += curr->ls[tn][0][0][0]->task_dy; - pictheight += TASK_VSEP; - } - pictheight += PICT_MONTHHEIGHT; - pictheight += PICT_TOPSEP ; - gantt_y = PICT_BOTSEP ; - gantt_dy = pictheight-PICT_TOPSEP-PICT_BOTSEP ; - - pictwidth=0; - pictwidth += PICT_LEFTSEP; - label_x = pictwidth; - pictwidth += DELIVRABLE_LABELWIDTH; - pictwidth += PICT_HSEP; - gantt_x = pictwidth ; - gantt_dx = 36*PICT_MONTHWIDTH ; - pictwidth += gantt_dx ; - pictwidth += PICT_HSEP; - title_x = pictwidth; - pictwidth += DELIVRABLE_TITLEWIDTH; - pictwidth += PICT_RIGHTSEP; - - fprintf(curr->os,"\\setlength{\\unitlength}{0.9mm}\n"); - fprintf(curr->os,"\\begin{picture}(%.1f,%.1f)\n",pictwidth,pictheight); - //print_hline(0,0,pictwidth,0); - //print_hline(0,pictheight,pictwidth,0); - task_box(pictwidth); - month_grid(gantt_x,gantt_y,gantt_dx,gantt_dy); - for ( tn=0 ; curr->ls[tn][0][0][0]!=0 ; tn++ ) { - task_delivrable(label_x,gantt_x,title_x,tn); - } - - print_milestones(gantt_x,0,gantt_dx,gantt_dy+gantt_y); - fprintf(curr->os,"\\end{picture}\n"); - fclose(curr->os); - curr->os=0; -} - -Tlivrable* do_partner_table_getLivrable(Tlivrable** leader, Tlivrable* top, int partner) -{ - int i; - Tlivrable* ret; - *leader=top->vers[top->nbvers-1]; - if (leader[0]->partner==partner) - return *leader; - for (i=0; inbpart ; i+=1) { - ret= top->part[i]; - if ( ret->partner==partner ) - return ret; - } - return 0; -} - -void do_partner_table_full(int partner) -{ - struct partner_def* part = partner_table+partner; - if ( (curr->os=fopen(part->fnfull,"w"))==0 ) { - fprintf(stderr,"can not open %s file for writing.\n",part->fnfull); - fprintf(stderr,"generation of %s partner table is skipped.\n",part->fnfull); - return; - } - fprintf(curr->os,"\\begin{tabular}{|c|l||r|r|r||r|}\\hline\n"); - fprintf(curr->os, - "number & \\multicolumn{1}{c||}{title} & \\multicolumn{3}{c||}{years } & total \\\\\\cline{3-5}\n"); - fprintf(curr->os, - " & & \\multicolumn{1}{c|}{1} & \\multicolumn{1}{c|}{2} & " - "\\multicolumn{1}{c||}{3} & \\\\\\hline\\hline\n"); - int tn,stn,dn,v=0; - double an1=0,an2=0,an3=0,an=0; - double tsk1,tsk2,tsk3,tsk; - int newlineadded=1; - for (tn=0 ; tnls[tn][0][0][0]==0) break; - if (tn!=0 && newlineadded==0 ) { - newlineadded = 1; - fprintf(curr->os,"\\hline "); - } - tsk1=tsk2=tsk3=tsk=0; - for (stn=0; stnls[tn][stn][dn][v]; - if (top==0) continue; - if ( (lcurr=do_partner_table_getLivrable(&leader,top,partner))==0 ) - continue; - double sum1,sum2,sum3,sum=0; - sum1 = lcurr->hman[0]; sum +=sum1; - sum2 = lcurr->hman[1]; sum +=sum2; - sum3 = lcurr->hman[2]; sum +=sum3; - char label_lnk[1000],label[1000],title[1000]; - gen_label_base(label,leader); - sprintf(label_lnk,"\\hyperlink{%s}{%s}",label,label); - sprintf(title,"\\resstablestyletitle{%s}",leader->title); - fprintf(curr->os,"%s & %s & %2.1f & %2.1f & %2.1f & %2.1f \\\\\\hline\n", - label_lnk,title,sum1,sum2,sum3,sum); - an1 += sum1 ; tsk1 += sum1 ; - an2 += sum2 ; tsk2 += sum2 ; - an3 += sum3 ; tsk3 += sum3 ; - an += sum ; tsk += sum ; - newlineadded=0; - if ( sum1==0 && leader->nbma[0]!=0) - fprintf(stderr,"ERROR: %-10s:%s probleme sur l'an 1 (in table=%2.1f, in gantt=%2.1f\n", - part->name,label,sum1,leader->nbma[0]); - else if (sum1!=0 && leader->nbma[0]==0 ) - fprintf(stderr,"ERROR: %-10s:%s probleme sur l'an 1 (in table=%2.1f, in gantt=%2.1f\n", - part->name,label,sum1,leader->nbma[0]); - else if (sum1!=0 && sum1>leader->nbma[0] ) - fprintf(stderr,"WARNING: %-10s:%s probleme sur l'an 1 (in table=%2.1f, in gantt=%2.1f\n", - part->name,label,sum1,leader->nbma[0]); - if ( sum2==0 && leader->nbma[1]!=0) - fprintf(stderr,"ERROR: %-10s:%s probleme sur l'an 2 (in table=%2.1f, in gantt=%2.1f\n", - part->name,label,sum2,leader->nbma[1]); - else if ( sum2!=0 && leader->nbma[1]==0) - fprintf(stderr,"ERROR: %-10s:%s probleme sur l'an 2 (in table=%2.1f, in gantt=%2.1f\n", - part->name,label,sum2,leader->nbma[1]); - else if (sum2!=0 && sum2>leader->nbma[1]) - fprintf(stderr,"WARNING: %-10s:%s probleme sur l'an 2 (in table=%2.1f, in gantt=%2.1f\n", - part->name,label,sum2,leader->nbma[1]); - if ( sum3==0 && leader->nbma[2]!=0) - fprintf(stderr,"ERROR: %-10s:%s probleme sur l'an 3 (in table=%2.1f, in gantt=%2.1f\n", - part->name,label,sum3,leader->nbma[2]); - else if ( sum3!=0 && leader->nbma[2]==0) - fprintf(stderr,"ERROR: %-10s:%s probleme sur l'an 3 (in table=%2.1f, in gantt=%2.1f\n", - part->name,label,sum3,leader->nbma[2]); - else if (sum3!=0 && sum3>leader->nbma[2]) - fprintf(stderr,"WARNING: %-10s:%s probleme sur l'an 3 (in table=%2.1f, in gantt=%2.1f\n", - part->name,label,sum3,leader->nbma[2]); - } - } - if (tsk!=0) - fprintf(curr->os,"%s & total Task-%d & %2.1f & %2.1f & %2.1f & %2.1f \\\\\\hline\n", - "",curr->ls[tn][0][0][0]->tn,tsk1,tsk2,tsk3,tsk); - - } - if ( an!=(an1+an2+an3) ) { - fprintf(stderr,"bad computation in %s table.\n",part->fnfull); - } - fprintf(curr->os,"\\hline\n"); - fprintf(curr->os,"%s & %s & %2.1f & %2.1f & %2.1f & %2.1f \\\\\\hline\n", - "","total",an1,an2,an3,an); - - fprintf(curr->os,"\\end{tabular}\n"); - fclose(curr->os); - curr->os=0; -} - -void do_partner_table_short(int partner) -{ - struct partner_def* part = partner_table+partner; - if ( (curr->os=fopen(part->fnshort,"w"))==0 ) { - fprintf(stderr,"can not open %s file for writing.\n",part->fnshort); - fprintf(stderr,"generation of %s partner table is skipped.\n",part->fnshort); - return; - } - fprintf(curr->os,"\\begin{center}\\begin{small}\\begin{tabular}{|c|l||r|r|r||r|}\\hline\n"); - fprintf(curr->os, - " & title & \\multicolumn{3}{c||}{years } & total \\\\\\cline{3-5}\n"); - fprintf(curr->os, - " & & \\multicolumn{1}{c|}{1} & \\multicolumn{1}{c|}{2} & " - "\\multicolumn{1}{c||}{3} & \\\\\\hline\\hline\n"); - int tn,stn,dn,v=0; - double an1=0,an2=0,an3=0,an=0; - double tsk1,tsk2,tsk3,tsk; - int newlineadded=1; - for (tn=0 ; tnls[tn][0][0][0]==0) break; - tsk1=tsk2=tsk3=tsk=0; - for (stn=0; stnls[tn][stn][dn][v]; - if (top==0) continue; - if ( (lcurr=do_partner_table_getLivrable(&leader,top,partner))==0 ) - continue; - double sum1,sum2,sum3,sum=0; - sum1 = lcurr->hman[0]; sum +=sum1; - sum2 = lcurr->hman[1]; sum +=sum2; - sum3 = lcurr->hman[2]; sum +=sum3; - an1 += sum1 ; tsk1 += sum1 ; - an2 += sum2 ; tsk2 += sum2 ; - an3 += sum3 ; tsk3 += sum3 ; - an += sum ; tsk += sum ; - newlineadded=0; - } - } - if (tsk!=0) - fprintf(curr->os,"Task-%d & %s & %2.1f & %2.1f & %2.1f & %2.1f \\\\\\hline\n", - curr->ls[tn][0][0][0]->tn, - task_names[curr->ls[tn][0][0][0]->tn],tsk1,tsk2,tsk3,tsk); - - } - if ( an!=(an1+an2+an3) ) { - fprintf(stderr,"bad computation in %s table.\n",part->fnshort); - } - fprintf(curr->os,"\\hline\n"); - fprintf(curr->os," & %s & %2.1f & %2.1f & %2.1f & %2.1f \\\\\\hline\n", - "total",an1,an2,an3,an); - - fprintf(curr->os,"\\end{tabular}\\end{small}\\end{center}\n"); - fclose(curr->os); - curr->os=0; -} - -void do_livrable_tables_open(int tablenum, int last) -{ - char fn[1024]; - - if (curr->os!=0) { - fprintf(curr->os,"\\end{tabular}\n"); - fclose(curr->os); - curr->os = 0; - } - - if ( last ) - return; - - sprintf(fn,"table_livrable_%02d.tex",tablenum); - if ( (curr->os=fopen(fn,"w"))==0 ) { - fprintf(stderr,"FATAL: can not open %s file for writing.\n",fn); - exit(1); - } - fprintf(curr->os,"\\begin{tabular}[t]{|l|c|c|c|p{\\desclen}|}\\hline\n"); - fprintf(curr->os,"number"); - fprintf(curr->os," & resp."); - fprintf(curr->os," & \\makebox[2mm]{T0+}"); - fprintf(curr->os," & \\makebox[2mm]{kind}"); - fprintf(curr->os," & description\\\\\\hline\\hline\n"); -} - -void do_livrable_tables(int maxlines) -{ - int nblines=maxlines; - int nbfile=1; - int tn,stn,dn,v; - do_livrable_tables_open(nbfile,0); nbfile +=1 ; - for (tn=0 ; tnls[tn][0][0][0]==0 ) break; - for (stn=0; stnls[tn][stn][0][0]==0 ) break; - for (dn=0; dnls[tn][stn][dn][0]; - if ( top==0 ) break; - Tlivrable* last=top->vers[top->nbvers-1]; - if ( (nblines-top->nbvers) <= 0 ) { - do_livrable_tables_open(nbfile,0); nbfile +=1 ; - nblines = maxlines; - } - for (v=0; vls[tn][stn][dn][v]; - if ( l==0 ) break; - if ( l->leader==0 ) continue; - char label_lnk[1000],label[1000],resp[100],date[100],kind[100],desc[1000]; - gen_label_full(label,l); - sprintf(label_lnk,"\\hyperlink{%s}{%s}",label,label); - sprintf(resp,"\\S%s",partner_table[l->partner].key); - sprintf(date,"\\makebox[2mm][r]{%d}",l->em); - sprintf(kind,"\\makebox[1mm]{%s}",l->kind); - if ( top->nbvers == 1 ) - sprintf(desc,"%s \\\\\\hline\n",last->title); - else if ( v==(top->nbvers-1) ) - sprintf(desc, - "\\multirow{-%d}{\\desclen}{%s}\\\\\\hline\n", - top->nbvers,last->title); - //else if ( v==(top->nbvers-1) ) - // sprintf(desc, "\\\\\\hline\n"); - else - sprintf(desc, "\\\\\\cline{1-4}\n"); - - fprintf(curr->os,"%-15s", label_lnk); - fprintf(curr->os," & %-10s", resp); - fprintf(curr->os," & %-30s", date); - fprintf(curr->os," & %-30s", kind); - fprintf(curr->os," & %s", desc); - nblines -= 1; - } - }}} - do_livrable_tables_open(nbfile,1); -} - -void do_effort_par_livrable(char* filename,int from_task, int to_task) -{ - //struct partner_def* part; - if ( (curr->os=fopen(filename,"w"))==0 ) { - fprintf(stderr,"can not open %s file for writing.\n",filename); - fprintf(stderr,"generation of %s file is skipped.\n",filename); - return; - } - fprintf(curr->os,"\\begin{tabular}{|l|l||c|r|r|r||r|}\\hline\n"); - fprintf(curr->os, - "number & \\multicolumn{1}{c||}{title} & part. & \\multicolumn{3}{c||}{years } & total \\\\\\cline{4-6}\n"); - fprintf(curr->os, - " & & & \\multicolumn{1}{c|}{1} & \\multicolumn{1}{c|}{2} & " - "\\multicolumn{1}{c||}{3} & \\\\\\hline\\hline\n"); - int tn,stn,dn,partner; - double an1=0,an2=0,an3=0,an=0; - for (tn=0 ; tnls[tn][0][0][0]==0) break; - for (stn=0; stnls[tn][stn][dn][0]; - if ( top==0 ) break; - if ( !( from_task<=top->tn && top->tn<=to_task ) ) break; - double liv1=0,liv2=0,liv3=0,liv=0; - for (partner=1 ; partner_table[partner].key!=0 ; partner+=1) { - Tlivrable *lcurr,*leader; - if ( (lcurr=do_partner_table_getLivrable(&leader,top,partner))==0 ) - continue; - double sum1,sum2,sum3,sum=0; - sum1 = lcurr->hman[0]; sum +=sum1; - sum2 = lcurr->hman[1]; sum +=sum2; - sum3 = lcurr->hman[2]; sum +=sum3; - char label_lnk[1000],label[1000],title[1000]; - gen_label_base(label,lcurr); - sprintf(label_lnk,"\\hspace{1.5cm}\\hyperlink{%s}{%s}",label,label); - sprintf(title,"\\resstablestyletitle{%s}",top->title); - fprintf(curr->os,"%s %10s & %50s & %10s & %2.1f & %2.1f & %2.1f & %2.1f \\\\\n", - linenb==0 ? "" : "\\cline{3-7}\n", - linenb==0 ? label_lnk : "", - linenb==0 ? title : "", - partner_table[lcurr->partner].key, - sum1,sum2,sum3,sum - ); - linenb += 1; - liv1 += sum1 ; st_sum1 += sum1 ; t_sum1 += sum1 ; an1 += sum1 ; - liv2 += sum2 ; st_sum2 += sum2 ; t_sum2 += sum2 ; an2 += sum2 ; - liv3 += sum3 ; st_sum3 += sum3 ; t_sum3 += sum3 ; an3 += sum3 ; - liv += sum ; st_sum += sum ; t_sum += sum ; an += sum ; - } - if (linenb>=0) { - livrablenb +=1; - task_n=top->tn; - subtask_n=top->stn; - if (linenb>1) { - fprintf(curr->os,"\\cline{3-7}\n"); - fprintf(curr->os,"%10s & %50s & %10s & %2.1f & %2.1f & %2.1f & %2.1f \\\\\\hline\n", - "","","total",liv1,liv2,liv3,liv); - } else - fprintf(curr->os,"\\cline{1-7}\n"); - } - } - if ( livrablenb>0) { - char name[100]; - char title[1000]; - sprintf(name,"\\hspace{0.5cm}st%d-%d",task_n,subtask_n); - sprintf(title,"\\resstablestyletitle{%s}",get_subtask_name(task_n,subtask_n)); - fprintf(curr->os,"%10s & %50s & %10s & %2.1f & %2.1f & %2.1f & %2.1f \\\\\\hline\n", - name,title,"total",st_sum1,st_sum2,st_sum3,st_sum); - subtasknb += 1; - } - } - if ( subtasknb>0 ) { - char name[100]; - char title[1000]; - sprintf(name,"task-%d",task_n); - sprintf(title,"\\resstablestyletitle{%s}",task_names[task_n]); - fprintf(curr->os,"%10s & %50s & %10s & %2.1f & %2.1f & %2.1f & %2.1f \\\\\\hline\\hline\n", - name,title,"total",t_sum1,t_sum2,t_sum3,t_sum); - } - } - fprintf(curr->os,"\\end{tabular}\n"); - fclose(curr->os); - curr->os=0; -} - -void do_partner_by_subtask() -{ - char filename[2000]; - int tn,stn,dn,partner; - for (tn=0 ; tnls[tn][0][0][0]==0) break; - for (stn=0; stnls[tn][stn][dn][0]; - if ( top==0 ) break; - double liv1=0,liv2=0,liv3=0,liv=0; - for (partner=1 ; partner_table[partner].key!=0 ; partner+=1) { - Tlivrable *lcurr,*leader; - if ( (lcurr=do_partner_table_getLivrable(&leader,top,partner))==0 ) { - continue; - } - parts[partner]=1; partnb+=1; - task_n = top->tn; - subtask_n = top->stn; - } - } - if (partnb==0) continue; - sprintf(filename,"tmp/st%d-%d-partner.tex",task_n,subtask_n); - if ( (curr->os=fopen(filename,"w"))==0 ) { - fprintf(stderr,"can not open %s file for writing.\n",filename); - fprintf(stderr,"generation of %s file is skipped.\n",filename); - continue; - } - for ( partner=1 ; partner_table[partner].key!=0 ; partner+=1) { - if ( parts[partner]==0) continue; - fprintf(curr->os,"\\S%s\n",partner_table[partner].key); - } - fclose(curr->os); - curr->os=0; - } - } -} - -#if 1 -void do_effort_par_livrable_xls(char* filename,int from_task, int to_task) -{ - //struct partner_def* part; - if ( (curr->os=fopen(filename,"w"))==0 ) { - fprintf(stderr,"can not open %s file for writing.\n",filename); - fprintf(stderr,"generation of %s file is skipped.\n",filename); - return; - } - int tn,stn,dn,partner; - fprintf(curr->os,"\"task\";\"sub-task\";\"delivrable\";"); - fprintf(curr->os,"\"cumul\";;;;"); - for ( partner=1 ; partner_table[partner].key!=0 ; partner+=1) { - fprintf(curr->os,"\"%s\";;;;",partner_table[partner].key); - } - fprintf(curr->os,"\"description\";\n"); - fprintf(curr->os,";;;"); - fprintf(curr->os,"\"an 1\";\"an 2\";\"an 3\";\"sum\";"); - for ( partner=1 ; partner_table[partner].key!=0 ; partner+=1) { - fprintf(curr->os,"\"an 1\";\"an 2\";\"an 3\";\"sum\";"); - } - fprintf(curr->os,";\n"); - double an1=0,an2=0,an3=0,anA=0; - double an1p[100], an2p[100], an3p[100], anAp[100]; - memset(an1p,0,sizeof(an1p)); memset(an2p,0,sizeof(an2p)); - memset(an3p,0,sizeof(an3p)); memset(anAp,0,sizeof(anAp)); - for (tn=0 ; tnls[tn][0][0][0]==0) break; - for (stn=0; stnls[tn][stn][dn][0]; - if ( top==0 ) break; - if ( !( from_task<=top->tn && top->tn<=to_task ) ) break; - double liv1=0,liv2=0,liv3=0,liv=0; - char label_lnk[1000],label[1000],title[1000]; - gen_label_base(label,top); - sprintf(label_lnk,"\\hyperlink{%s}{%s}",label,label); - sprintf(title,"%s",top->title); - double sum1p[20], sum2p[20], sum3p[20], sumAp[20]; - memset(sum1p,0,sizeof(sum1p)); memset(sum2p,0,sizeof(sum2p)); - memset(sum3p,0,sizeof(sum3p)); memset(sumAp,0,sizeof(sumAp)); - task_n=top->tn; - subtask_n=top->stn; - for (partner=1 ; partner_table[partner].key!=0 ; partner+=1) { - Tlivrable *lcurr,*leader; - if ( (lcurr=do_partner_table_getLivrable(&leader,top,partner))==0 ) - continue; - double sum1,sum2,sum3,sum=0; - sum1 = lcurr->hman[0]; sum +=sum1; - sum2 = lcurr->hman[1]; sum +=sum2; - sum3 = lcurr->hman[2]; sum +=sum3; - linenb += 1; - liv1 += sum1 ; st_sum1 += sum1 ; t_sum1 += sum1 ; an1 += sum1 ; - liv2 += sum2 ; st_sum2 += sum2 ; t_sum2 += sum2 ; an2 += sum2 ; - liv3 += sum3 ; st_sum3 += sum3 ; t_sum3 += sum3 ; an3 += sum3 ; - liv += sum ; st_sumA += sum ; t_sumA += sum ; anA += sum ; - sum1p[partner] += sum1 ; st_sum1p[partner] += sum1 ; t_sum1p[partner] += sum1 ; an1p[partner] += sum1 ; - sum2p[partner] += sum2 ; st_sum2p[partner] += sum2 ; t_sum2p[partner] += sum2 ; an2p[partner] += sum2 ; - sum3p[partner] += sum3 ; st_sum3p[partner] += sum3 ; t_sum3p[partner] += sum3 ; an3p[partner] += sum3 ; - sumAp[partner] += sum ; st_sumAp[partner] += sum ; t_sumAp[partner] += sum ; anAp[partner] += sum ; - } - if (linenb>=1) { - livrablenb+=1; - fprintf(curr->os,";;\"%s\";",label); - fprintf(curr->os,"%2.1f;%2.1f;%2.1f;%2.1f;",liv1,liv2,liv3,liv); - for ( partner=1 ; partner_table[partner].key!=0 ; partner+=1) { - fprintf(curr->os,"%2.1f;%2.1f;%2.1f;%2.1f;", - sum1p[partner],sum2p[partner],sum3p[partner],sumAp[partner]); - } - fprintf(curr->os,"\"%s\";",title); - fprintf(curr->os,"\n"); - } - } - if ( livrablenb>0) { - subtasknb += 1; - char name[100]; - char title[1000]; - sprintf(name,"st%d-%d",task_n,subtask_n); - sprintf(title,"%s",get_subtask_name(task_n,subtask_n)); - fprintf(curr->os,";\"%s\";;",name); - fprintf(curr->os,"%2.1f;%2.1f;%2.1f;%2.1f;",st_sum1,st_sum2,st_sum3,st_sumA); - for ( partner=1 ; partner_table[partner].key!=0 ; partner+=1) { - fprintf(curr->os,"%2.1f;%2.1f;%2.1f;%2.1f;", - st_sum1p[partner],st_sum2p[partner],st_sum3p[partner],st_sumAp[partner]); - } - fprintf(curr->os,"\"%s\";",title); - fprintf(curr->os,"\n"); - } - } - if ( subtasknb>0 ) { - char name[100]; - char title[1000]; - sprintf(name,"task-%d",task_n); - sprintf(title,"%s",task_names[task_n]); - fprintf(curr->os,"\"%s\";;;",name); - fprintf(curr->os,"%2.1f;%2.1f;%2.1f;%2.1f;",t_sum1,t_sum2,t_sum3,t_sumA); - for ( partner=1 ; partner_table[partner].key!=0 ; partner+=1) { - fprintf(curr->os,"%2.1f;%2.1f;%2.1f;%2.1f;", - t_sum1p[partner],t_sum2p[partner],t_sum3p[partner],t_sumAp[partner]); - } - fprintf(curr->os,"\"%s\";",title); - fprintf(curr->os,"\n"); - } - } - char name[100]; - char title[1000]; - sprintf(name,"total"); - sprintf(title,"%s",""); - fprintf(curr->os,"\"%s\";;;",name); - fprintf(curr->os,"%2.1f;%2.1f;%2.1f;%2.1f;",an1,an2,an3,anA); - for ( partner=1 ; partner_table[partner].key!=0 ; partner+=1) { - fprintf(curr->os,"%2.1f;%2.1f;%2.1f;%2.1f;", - an1p[partner],an2p[partner],an3p[partner],anAp[partner]); - } - fprintf(curr->os,"\"%s\";",title); - fprintf(curr->os,"\n"); - fclose(curr->os); - curr->os=0; -} -#endif - -int main() -{ - int tnplus[10] = { 1, 2, 3, 4, 5, 6, -1 }; - int tnmoins[10] = { 1, 2, 3, 4, 5, 6, -1 }; - - yylex(); - do_gantt("gantt.tex",0,0); - do_gantt("gantt1.tex",tnplus,0); - do_gantt("gantt2.tex",0,tnmoins); - - curr = data_new(0,0); - prepare0(curr); - prepare1(curr); - prepare2(curr); - prepare3(curr); - do_partner_table_full(1); do_partner_table_short(1); - do_partner_table_full(2); do_partner_table_short(2); - do_partner_table_full(3); do_partner_table_short(3); - do_partner_table_full(4); do_partner_table_short(4); - do_partner_table_full(5); do_partner_table_short(5); - do_partner_table_full(6); do_partner_table_short(6); - do_partner_table_full(7); do_partner_table_short(7); - do_partner_table_full(8); do_partner_table_short(8); - - curr = data_new(0,0); - prepare0(curr); - prepare1(curr); - prepare2(curr); - prepare3(curr); - do_livrable_tables(44); - - curr = data_new(0,0); - prepare0(curr); - prepare1(curr); - prepare2(curr); - prepare3(curr); - do_effort_par_livrable("tmp/effort-par-livrable-1.tex",1,2); - do_effort_par_livrable("tmp/effort-par-livrable-2.tex",3,5); - do_effort_par_livrable("tmp/effort-par-livrable-3.tex",6,7); - do_effort_par_livrable("tmp/effort-par-livrable-4.tex",8,8); - do_effort_par_livrable_xls("tmp/effort-par-livrable.csv",1,8); - - curr = data_new(0,0); - prepare0(curr); - prepare1(curr); - prepare2(curr); - prepare3(curr); - do_partner_by_subtask(); - return 0; -} Index: r/section-1.tex =================================================================== --- /anr/section-1.tex (revision 386) +++ (revision ) @@ -1,45 +1,0 @@ -% -The market of digital systems is about 4,600 M\$ today and is estimated to 5,600 M\$ in 2012. However the ever growing applications complexity involves integration of heterogeneous technologies and requires the design of complex Multi-Processors System on Chip (MPSoC). During the last decade, the use of ASICs appeared to be more and more reserved to high volume markets, because the design and fabrication costs of such components exploded, due to increasing NRE (Non Recurring-Engineering) costs. Fortunately, recent FPGA components, such as the Virtex5-6 family from XILINX or the Stratix4 family from ALTERA, can nowadays implement a complete MPSoC with multiple processors and several dedicated coprocessors for a few Keuros per device. -\parlf -Many applications are initially captured algorithmically in High-Level Languages -(HLLs) such as C/C++. This has led to growing interest in tools that can provide -an implementation path directly from HLLs to hardware. Thus, Electronic System -Level (ESL) design methodologies (Virtual Prototyping, Co-design, High-Level -Synthesis...) are now mature but don’t allow still the full automation of a -system-level design flow. -Unfortunately, ESL tool development today has primarily focused on the design of -hardwired devices i.e. ASICs and ASSPs (Application Specific Standard Product). -However, the increasing sophistication of FPGAs has accelerated the need for -FPGA-based ESL design methodologies. ESL methodologies hold the promise of -streamlining the design approach by accepting designs written in C/C++ language -and implementing the function straight into FPGA. Coupling FPGA technologies and -ESL methodologies will allow both SMES and major companies to design innovative -devices and to enter new, low and medium volume markets. Furthermore, today -there is an increasing industrial interest in IC that integrates both hardwired -CPU cores or MPSoC and a configurable area (FPGA) such as Intel-ATOM E600C. In a -few years, such chips will surely be used in embedded systems and even standard -general purpose CPU cores will contains a configurable area. -This will make possible to target low and medium volume markets of digital -system and probably explode the indusrial activity of this markets. -\parlf -COACH is aligned with this long term vision, which requires an integrated design flow for the digital multiprocessors systems, targeting FPGAs and dedicated to the system and software designers; this project do not hope to solve all related issues, but aims at specifying and implementing innovative technological elements of the required tool chain. It will be dedicated to system/software designers, and hide as much as possible the hardware characteristics to the end-user. COACH will mainly target three kinds of digital systems: 1/ Embedded and autonomous application (personal digital assistants , ambient computing components, wireless sensor networks) 2/ mixed systems (CPU + FPGA extension boards) to accelerate a specific application answering High-Performance Computing (HPC) and High-Speed Signal Processing needs, 3/ Sub-system IP to be integrating into a larger system. -\\ -The COACH open-source environment will integrate several hardware and software technologies: -% -\begin{itemize} -\item Design Space Exploration by allowing to describe an application as a process network i.e. a set of tasks communicating through FIFO channels and to map the application on a shared-memory, MPSoC architecture -\item High Level Synthesis of hardware accelerators -\item Platform based design: three architectural templates will be provided (free-generic, ALTERA and XILINX’s IPs based) -\item Hardware/Software communication middleware by implementing an homogeneous HW/SW communication infrastructure and communication API, that will be used for communications between software tasks running on embedded processors and dedicated hardware coprocessors -\item IP based design: using IP-XACT standard for describing the components of the architectural template and by providing the IP-XACT description of the generated MPSoC -\end{itemize} -% -Finally, a large number of SMEs and large companies, (see "letters of interest" Annex \ref{lettre-soutien}), -have expressed their interest for this project: -\altera, FLEXRAS, INPIXAL, CAMKA System, RENESAS Design, EADS-ASTRIUM, -CONTINENTAl, TEAMCAST, ALSIM NAVTEL Systems. -\altera, a major FPGA company provides FPGA boards to the project. -These companies are either FPGA providers (engaged to collaborate by delivering FPGA board to partners), -design houses, EDA companies, or system integrators. -This heterogeneity of actors show the strong added value brought by the COACH platform. - Index: r/section-2.tex =================================================================== --- /anr/section-2.tex (revision 386) +++ (revision ) @@ -1,82 +1,0 @@ -Embedded systems (SoC and MPSoC) have become an inevitable evolution in the microelectronic industry. -The ASIC technology (Application Specific Integrated Circuits) -is not an option for markets with small series of products due to RNE costs. -Fortunately, the new FPGA (Field Programmable Gate Array) components, -such as the Virtex6 family from \xilinx, or the Stratix4 family from \altera can implement a complete -multi-processor architecture on a single device. -But the design of embedded system is a long and complex task that requires expertise in software, -software/hardware portioning, operating system, hardware design, VHDL/Verilog modeling. -Only very few SMEs have these multiple expertises and are present on the embedded system market. -The corresponding development cost is high and it is not compliant with -specification or standard evolution (problem of flexibility). -Furthermore, even small design shops in big companies are facing the same issue. -\begin{center}\begin{minipage}{.8\linewidth}\textit{ -The major objective of COACH is to provide to system designers, an affordable -open-source framework to design embedded systems on FPGA devices. -}\end{minipage}\end{center} -%Current design methodologies provide quite low-level abstraction capabilities, and -%there is an urgent need to leverage system level exploration through the use of a high-level -%specification of the application and design space exploration tools. -%The first system oriented approaches are appearing, among which those -%based on C/C++ and SystemC are the most popular, but few of them are specifically targetting FPGAs. -%%% -% -The COACH project will propose a new design flow based on a small number of architectural templates. -An architectural template is a generic, parameterized architecture, relying on a predefined library -of IP cores. -Besides using a specific collection of general purpose IP cores (such as processors cores, -embedded memory controllers, system bus controllers, I/O and peripheral controllers), each architectural -template can be enriched by dedicated hardware coprocessors, obtained by high level synthesis (HLS) tools. -During this project, the COACH partners will develop three different architectural templates: -\begin{enumerate} -\item An \altera architectural template based on the \altera IP core library, - the AVALON system bus and the NIOS processor. -\item A \xilinx architectural template based on the \xilinx IP core library, the - \xilinxbus system bus and the \xilinxcpu processor. -\item A Neutral architectural template based on the SoCLib IP core library and the VCI/OCP - communication infrastructure. -\end{enumerate} -%The proposed design flow starts from a high level description of the application, specified as a set of -%parallel tasks written in C, without any assumption on the hardware or software implementation -%of these tasks. It lets the system -%designer in charge of expressing the coarse grain parallelism of the application, gives the designer -%the possibility to explore various mapping of the application on the selected template architecture, -%and offers a high predictability of results with respect to cost and performance objectives. -%\\ -%When this interactive, system level, design space exploration is completed (converging to -%a specific mapping on a specific version of the selected architectural template), the rest of the flow -%is fully automated: the synthesizable VHDL models for the various hardware components, as well as the binary -%code for the software running on the embedded processors, and the bit-stream to program the target FPGA -%will be automatically generated by the COACH tools. -%% -%\parlf -%The strength of the COACH approach is the strong integration of the high-level synthesis tools -%in a platform based design flow supporting virtual prototyping and design space exploration. -%Most building blocks already exist (resulting from previous projects): the GAUT -%or UGH synthesis tools, the DNA embedded operating systems, the ASIP technology, -%the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelization tool, -%as well as the SoCLib library of SystemC simulation models. -%They must now be enhanced and integrated in a consistent design flow: this will -%be done in Magillem framework thanks to the IP-XACT standard. -%%The five academic laboratories worked very closely during more than one year (one monthly meeting -%%in Paris from january 2009 to february 2010, to analyse the issues of interfacing and integrating -%%those various technologies, and to define the detailed architecture of the proposed design flow. -%%%% -% -In HPC (High Performance Computing), the targeted application is an existing one -running on a PC. -The COACH framework helps designers to accelerate it by migrating critical parts into a -SoC embedded into an FPGA device plugged to the PC PCI/X bus. -\begin{center}\begin{minipage}{.8\linewidth}\label{HPC:definition}\textit{ -The second objective of COACH is to extend the framework for HPC applications. -}\end{minipage}\end{center} -This will allow SMEs to enter the HPC market for applications that are -unadapted to the current GPU based solutions. -\parlf -COACH generates SoCs which are part of larger systems. Thus it is important to take -into account the existing industrial design flow. For this reason COACH will use the -IP-XACT IEEE 1685 standard for packaging these generated SoCs. -\begin{center}\begin{minipage}{.8\linewidth}\textit{ -The third objective of COACH is to facilitate the integration of generated SoC in global system design flow. -}\end{minipage}\end{center} -%%% Index: r/section-consortium-desc.tex =================================================================== --- /anr/section-consortium-desc.tex (revision 386) +++ (revision ) @@ -1,313 +1,0 @@ -\anrdoc{(maximum 0,5 page par partenaire) Decrire brievement chaque -partenaire et fournir ici les elements permettant d'apprecier la -qualification des partenaires dans le projet (le \og pourquoi qui fait quoi -\fg). Il peut s'agir de realisations passees, d'indicateurs (publications, -brevets), de l'interet du partenaire pour le projet.\\ -Montrer la complementarite et la valeur ajoutee des cooperations entre les -differents partenaires. L'interdisciplinarite et l'ouverture à diverses -collaborations seront à justifier en accord avec les orientations du -projet. (1 page maximum)} - -The consortium is made of 8 partners: 5 academic and 3 industrial, which is well balanced -for reaching the objectives (technical innovation and industrial evaluation for further exploitation). -Each academic partner is expert in a few area and each industrial brings a -different approach to the use of the tools. -\parlf -The expertise domains of academic partners are -MPSoC design \& virtual prototyping (\upmc, \tima), -micro-architecture design (\upmc, \tima, \ubs), -HLS (\upmc, \tima, \ubs), -embedded OS (\tima), -compilation (\ubs, \lip), -polyhedral model (\lip), -HPC (\lip, \upmc) and -ASIP design (\inria). -These domains cover all the COACH aspects. -\parlf -The approach to the use of the tools by industrials are: -IP-XACT and industrial flow integration (\mds), -HPC (\bull) and IP integration in SoC design flow (\mds, \thales). -\thales will represent the FPGA users, \bull the HPC users, and \mds the SoC integrators. - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsubsection{\mdslong} - -Magillem Design Services has been established by a team of seasoned engineers and a -group of business angels in the fall of 2006. The company has inherited Magillem, a -robust and innovative technology worth 120 man years. The Magillem environment is -dedicated to the design, verification and flow management of complex HW/SW based on IP-XACT. -In the service area, we audit the existing industrial flows and propose a work plan to -adapt them to IP-XACT, we validate and verify the full compatibility of tools interfaces -into a flow testbench, we test the IP deliverables against a benchmark for compliance -using our IP-XACT packager, and check IP integration properties onto a test system. -Magillem's tools are used in the most advanced production flows of integrated circuit -manufacturers (ST, NXP, TI, Qualcomm, etc.) and are linked with the research work of -the best laboratories of the domain (LIP6, TIMA, Fhg, OFFIS, etc.). Our participation -to leading European collaborative projects (e.g. IST COMPLEX, SPRINT, ICODES, etc.) -allow us to maintain a high level of innovation around our core technology: SoC design -methodologies at ESL, design and verification in AMS domain, HW/SW co-design, safety -and security of systems. -Beyond this core technology domain, Magillem has evolved with the tool suite called -Revenge, answering to wider assembly issues for large heterogeneous systems. - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsubsection{\upmc} - -University Pierre et Marie Curie (UPMC) is the largest university in France (7400 -employees, 38000 students). -The Laboratoire d'Informatique de Paris 6 (LIP6) is the computer science laboratory of -UPMC, hosting more than 400 researchers, under the umbrella of the CNRS (Centre National -de la Recherche Scientifique). -The \og System on Chip \fg Department of LIP6 consists of 40 permanent -researchers and 40 PHD students. -The research focuses on CAD tools and methods for VLSI and System on Chip design. -\parlf -The SoC department has been involved in several projects: IDPS, EVEREST, -OMI-HIC/MACRAME/\-ARCHES, EUROPRO, COSY, Medea SMT/MESA/+, BDREAMS, SoCLib, TSAR. -It developed and maintains the public domain VLSI CAD system ALLIANCE that is installed in more than -200 universities worldwide. It is also in charge of the SoCLib technical -coordination and WEB server. -\parlf -Even if the preferred dissemination policy for the COACH design flow will be the free -software policy, the SoC department is ready to support start-ups : -Six startup companies have been created by former -researchers from the SoC department of LIP6 between 1997 and 2002. -%The annual budget is about 3 M{\texteuro}, and 1.5 M{\texteuro} are from research contracts. -%The SoCLib DSX component was designed and developped in our laboratory. -%It allows design space exploration and will the base of the $CSG$ COACH tools. -%Moreover, the LIP6 developed during the last 10 years the UGH tool for high level -%synthesis of control-dominated coprocessors. -%This tool will be modified to be integrated in the COACH design flow. - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsubsection{\ubs} - -The Lab-STICC (Laboratoire des Sciences et Techniques de l'Information, -de la Communication, et de la Connaissance), is a French CNRS laboratory -(UMR 3192) that groups 4 research centers in the west and south -Brittany. -%: the Universit\'e de Bretagne-Sud (UBS), the Universit\'e de -%Bretagne Occidentale (UBO), and Telecom Bretagne (ENSTB). -%The Lab-STICC is composed of three departments: Microwave and equipments (MOM), -%Digital communications, Architectures and circuits (CACS) and Knowledge, -%information and decision (CID). -It represents a staff of 279 peoples, including 115 researchers and 113 PhD -students. -The scientific production during the last 4 years represents 20 -books, 200 journal publications, 500 conference publications, 22 -patents and 69 PHDs diploma. -\parlf -%The UBS/Lab-STICC laboratory is involved in several national research -%projects (e.g. RNTL : SystemC'Mantic, EPICURE - RNRT : MILPAT, ALIPTA, -%A3S - ANR : MoPCoM, SoCLib, Famous, RaaR, AFANA, Open-PEOPLE, ICTER ...), -%CMCU project (COSIP) and regional projects (e.g. ITR projects PALMYRE -%...). It is also involved in European Project (e.g. ITEA/SPICES, -%IST/AETHER ...). -The UBS/Lab-STICC laboratory is involved in several projects (SystemC'Mantic, -EPICURE, MILPAT, ALIPTA, A3S, MoPCoM, SoCLib, Famous, RaaR, AFANA, Open-PEOPLE, -ICTER, COSIP, PALMYRE, ITEA/SPICES, IST/AETHER. -%These projects are conducted through tight cooperation -%with national and international companies and organizations (e.g. France -%Telecom CNET, MATRA, CEA, ASTRIUM, \thales Com., \thales Avionics, AIRBUS, -%BarCo, STMicroelectronics, Alcatel-Lucent ...). -%Results of those or former -%projects are for example the high-level synthesis tool GAUT, the UHLS -%syntax and semantics-oriented editor, the DSP power estimation tool -%Soft-explorer or the co-design framework Design Trotter. -\parlf -The CACS department of the Lab-STICC (also referred as UBS/Lab-STICC), -located in Lorient, is involved in COACH. -The UBS/Lab-STICC is working on the design of complex electronic systems -and circuits, especially but not exclusively focussing on real-time -embedded systems, power and energy consumption optimization, high-level -synthesis and IP design, digital communications, hardware/software -co-design and ESL methodologies. The application targeted by the -UBS/Lab-STICC are mainly from telecommunication and multimedia domains -which enclose signal, image, video, vision, and communication processing. - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsubsection{\liplong} -The Compsys group of Ecole Normale Sup\'erieure de Lyon is a project-team -of INRIA Rh\^one-Alpes and a part of Laboratoire de l'Informatique du -Parall\'elisme (LIP), UMR 5668 of CNRS. It has four permanent researchers -and a variable number of PhD students and post-docs. Its field of -expertise is compilation for embedded system, optimizing compilers -and automatic parallelization. Its members were among the initiators -of the polyhedral model for automatic parallelization and program -optimization generally. It has authored or contributed to -several well known libraries for linear programming, polyhedra manipulation -and optimization in general. It has strong industrial cooperations, notably -with ST Microelectronics and \thales. - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsubsection{\tima} -The TIMA laboratory ("Techniques of Informatics and Microelectronics -for integrated systems Architecture") is a public research laboratory -sponsored by Centre National de la Recherche Scientifique (CNRS, UMR5159), -Grenoble Institute of Technology (Grenoble-INP) and Universit\'{e} Joseph Fourier -(UJF). -The research topics cover the specification, design, verification, test, -CAD tools and design methods for integrated systems, from analog and -digital components on one end of the spectrum, to multiprocessor -Systems-on-Chip together with their basic operating system on the other end. -\parlf -Currently, the lab employs 124 persons among which 60 PhD candidates, and runs -32 ongoing French/European funded projects. -Since its creation in 1984, TIMA funded 7 startups, patented 36 inventions -and had 243 PhD thesis defended. -\parlf -The System Level Synthesis Group (25 people including PhDs) is -involved in several FP6, FP7, CATRENE and ANR projects. -Its field of expertise is in CAD and architecture for Multiprocessor -SoC and Hardware/Software interface. - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsubsection{\inria} - -INRIA, the French national institute for research in computer science -and control, operating under the dual authority of the Ministry of -Research and the Ministry of Industry, is dedicated to fundamental and -applied research in information and communication science and -technology (ICST). -It has workforce of 3800 persons that work in 168 joint research project-teams. -\parlf -The Institute plays a major role in technology -transfer by fostering training through research, diffusion of -scientific and technical information, development, as well as -providing expert advice and participating in international programs. -Being in close contact with industry, INRIA is a major participant in -the development of ICST in France. -\parlf -The CAIRN group of INRIA Rennes -- Bretagne Atlantique study reconfigurable -system-on-chip, i.e. hardware systems whose configuration may change before or even during -execution. -To this end, CAIRN has 13 permanent researchers and a variable number of PhD -students, post-docs and engineers. -CAIRN intends to approach reconfigurable architectures from three -angles: the invention of new reconfigurable platforms, the development -of associated transformation, compilation and synthesis tools, and the -exploration of the interaction between algorithms and architectures. -CAIRN is a joint team with CNRS, University of Rennes 1 and ENS Cachan. -%By playing a leading role in the scientific community in the field and -%Throughout its eight research centres in Rocquencourt, Rennes, Sophia Antipolis, -%Grenoble, Nancy, Bordeaux, Lille and Saclay, INRIA has a workforce of 3800, 2800 -%of whom are scientists from INRIA and INRIA's partner organizations such as CNRS -%(the French National Center for Scientific Research), universities and leading -%engineering schools. -%They work in 168 joint research project-teams. -%Many INRIA researchers are also professors and approximately 1 000 doctoral -%students work on theses as part of INRIA research project-teams. -%\parlf -%INRIA develops many partnerships with industry and fosters technology -%transfer and company foundation in the field of ICST - some ninety -%companies have been founded with the support of INRIA-Transfert, a -%subsidiary of INRIA, specialized in guiding, evaluating, qualifying, -%and financing innovative high-tech IT start-up companies. INRIA is -%involved in standardization committees such as the IETF, ISO and the -%W3C of which INRIA was the European host from 1995 to 2002. -%\parlf -%INRIA maintains important international relations and exchanges. In -%Europe, INRIA is a member of ERCIM which brings together research -%institutes from 19 European countries. INRIA is a partner in about 120 -%FP6 actions and 40 FP7 actions, mainly in the ICST field. INRIA also -%collaborates with numerous scientific and academic institutions abroad -%(joint laboratories such as LIAMA, associated research teams, training -%and internship programs). - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsubsection{\bull} - -\bull designs and develops servers and software for an open environment, integrating the -most advanced technologies. It brings to its customers its expertise and know-how to help -them in the transformation of their information systems and to optimize their IT -infrastructure and their applications. -\\%\parlf -\bull is particularly present in the public sector, banking, finance, telecommunication -and industry sectors. Capitalizing on its wide experience, the Group has a thorough -understanding of the business and specific processes of these sectors, thus enabling it to -efficiently advise and to accompany its customers. Its distribution network spreads to -over 100 countries worldwide. -\parlf -The team participating to the COACH project is from the Server Development Department -based in Les Clayes-sous-Bois, France. The SD Department is in charge of developing -hardware for open servers (e.g. NovaScale) and HPC solutions. Its main activities range -from architecture specification, ASIC design/verification/prototyping to board design and -include also specific EDA development to complement standard tools. - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsubsection{\thales} - -\thales is a world leader for mission critical information systems, with activities in 3 -core businesses (aerospace, defence, security). -It employs 68000 people worldwide, and is present in 50 countries. -TRT (\thales Research \& Technology) operates at the corporate level as the technical -community network architect, in charge of developing upstream and \thales-wide -R\&T activities, with vision and visibility. -In support of \thales applications, TRT's mission is also to anticipate and -speed up technology transfer from research to development in Divisions by -developing collaborations in R\&T. -%\thales is international, but Europe-centered. -%Research \& Development activities are disseminated, and corporate Research and -%Technology is concentrated in Centres in France, the United Kingdom and the -%Netherlands. -%A key mission of our R\&T centres is to have a bi-directional transfer, or -%"impedance matching" function between the scientific research network and the -%corresponding businesses. -%The TRT's Information Science and Technology Group is able to develop innovative -%solutions along the information chain exploiting sensors data, through expertise -%in: computational architectures in embedded systems, typically suitable for -%autonomous system environments, mathematics and technologies for decision -%involving information fusion and cognitive processing, and cooperative -%technologies including man system interaction. -The Embedded System Laboratory (ESL) involved in the COACH project is part of -TRT, it is based in Palaiseau (France). -\parlf -Like other labs of TRT, ESL is in charge of making the link between the needs -from \thales business units and the emerging technologies, in particular through -assessment and de-risking studies. -It has a long experience on parallel architectures design, in particular on SIMD architectures used for -image processing and signal processing applications and on reconfigurable architectures. -ESL is also strongly involved in studies on programming tools for these types of -architectures and has developed the SpearDE tool used in this project. -\parlf -The laboratory has coordinated the FP6 IST MORPHEUS project on reconfigurable -technology.% being highly involved in the associated programming toolset. -The team has also been involved in the FP6 IST FET AETHER project on -self-adaptability technologies and coordinated national projects on MPSoC -architecture and tools like the Ter\verb+@+ops project (P\^{o}le de -Comp\'{e}titivit\'{e} System\verb+@+tic). %dedicated to the design of a MPSoC for intensive computing embedded systems. -% -%\thales is a world leader for mission critical information systems, with activities in 3 -%core businesses: aerospace (with all major aircraft manufacturers as customers), defence, -%and security (including ground transportation solutions). It employs 68000 people -%worldwide, and is present in 50 countries. \thales Research \& Technology operates at the -%corporate level as the technical community network architect, in charge of developing -%upstream and \thales-wide R \& T activities, with vision and visibility. In support of -%\thales applications, TRT's mission is also to anticipate and speed up technology transfer -%from research to development in Divisions by developing collaborations in R\&T. \thales is -%international, but Europe-centered. Research \& Development activities are disseminated, -%and corporate Research and Technology is concentrated in Centres in France, the United -%Kingdom and the Netherlands. A key mission of our R\&T centres is to have a bi-directional -%transfer, or "impedance matching" function between the scientific research network and the -%corresponding businesses. The TRT's Information Science and Technology Group is able to -%develop innovative solutions along the information chain exploiting sensors data, through -%expertise in: computational architectures in embedded systems, typically suitable for -%autonomous system environments, mathematics and technologies for decision involving -%information fusion and cognitive processing, and cooperative technologies including man -%system interaction. -%\parlf -%The Embedded System Laboratory (ESL) of TRT involved in the COACH project is part of the -%Information Science and Technology Group. Like other labs of TRT, ESL is in charge of -%making the link between the needs from \thales business units and the emerging -%technologies, in particular through assessment and de-risking studies. It has a long -%experience on parallel architectures design, in particular on SIMD architectures used for -%image processing and signal processing applications and on reconfigurable architectures. -%ESL is also strongly involved in studies on programming tools for these types of -%architectures and has developed the SpearDE tool used in this project. The laboratory had -%coordinated the FP6 IST MORPHEUS project on reconfigurable technology, being highly -%involved in the associated programming toolset. The team has also been involved in the FP6 IST -%FET AETHER project on self-adaptability technologies and coordinated national projects on -%MPSoC architecture and tools like the Ter\verb+@+ops project (P\^{o}le de -%Comp\'{e}titivit\'{e} System\verb+@+tic) dedicated to the design of a MPSoC for intensive -%computing embedded systems. - Index: r/section-consortium-leader.tex =================================================================== --- /anr/section-consortium-leader.tex (revision 386) +++ (revision ) @@ -1,19 +1,0 @@ -\anrdoc{(0,5 page maximum)\\ -Fournir les elements permettant de juger la capacite du coordinateur à -coordonner le projet.} - -Emmanuel Vaumorin is responsible for research and development program at MDS. Since 2003, -he is managing the realization of work for more than 12 projects (IST, MEDEA+, CATRENE, ANR, FUI, etc.). -Emmanuel is a contributing member in the IP-XACT working group of ACCELERA. -In 2002-2005, Emmanuel was project manager of the project SystemC'mantic in -the former call RNTL. The main objective was to set up a design and verification environment -based on the new language SystemC and to introduce new techniques for system level design. -The partners of this project were Thales, CEA-LIST, TIMA, LESTER. -This project has reached all its objectives in time and has been well ranked by the reviewers. -In 2002-2003 he was product manager for an ESL design and verification -environment based on SystemC. Emmanuel is a graduate of Conservatoire -National des Arts et M\'etiers in the field of digital electronics for communications. -Emmanuel contributed to the publication of 10 white papers in the ESL design -flow management area. -Emmanuel is one of the co-founders of \mds. - Index: r/section-consortium-people.tex =================================================================== --- /anr/section-consortium-people.tex (revision 386) +++ (revision ) @@ -1,109 +1,0 @@ -\anrdoc{(2 pages maximum)\\ -Qualifier les personnes, preciser leurs activites principales et leurs competences propres. -Pour chaque partenaire remplir le tableau ci-dessous.\\ -Pour chacune des personnes dont l'implication dans le projet est superieure a -25\% de son temps sur la totalite du projet (c'est-a-dire une moyenne de 3 -hommes.mois par annee de projet), une biographie d'une page maximum sera placee -en annexe 7.2 du present document qui comportera: -\begin{itemize} -\item Nom, prenom, age, cursus, situation actuelle -\item Autres experiences professionnelles -\item Liste des cinq publications (ou brevets) les plus significatives des - cinq dernieres annees, nombre de publications dans les revues - internationales ou actes de congres a comite de lecture. -\item Prix, distinctions -\end{itemize} -Si besoin, pour chacune des personnes, leur implication dans d'autres projets -(Contrats publics et prives effectues ou en cours sur les trois dernieres -annees) sera presentee selon le modele fourni en annexe. Les tableaux seront -places en annexe 7.3. On precisera l'implication dans des projets europeens ou -dans d'autres types de projets nationaux ou internationaux. Expliciter -l'articulation entre les travaux proposes et les travaux anterieurs ou deja en -cours.} - -\def\doNote#1#2{{\scriptsize-- $^{#1}$#2}} -\def\doAbre#1#2{{\mbox{#2$^{#1}$}}\xspace} - -\def\TL#1{\textcolor{blue}{#1 (L)}} -The table in Figure~\ref{involved:people} lists the people involved in the -project. -The first column indicates the role of the person in the project -(C:global leader, L:local leader, M:contributor) -and a task number with a 'L' flag (e.g.: \TL{3}) in the last column indicates that the person -is its leader. -\begin{figure}[t!] -\newenvironment{peopletabular}{% - \let\PMnote\relax \def\PM{\doAbre{\ast}{PM}\gdef\PMnote{\doNote{\ast}{total of PM for the 3 years of the project.}}} - \let\COnote\relax \def\CO{\textcolor{red}{C}}%{\doAbre{a}{coor.}\gdef\COnote{\doNote{a}{coordinator.}}} - \let\REnote\relax \def\RE{\textcolor{blue}{L}}%{\doAbre{b}{resp.}\gdef\REnote{\doNote{b}{responsible.}}} - \let\MEnote\relax \def\ME{M}%{\doAbre{c}{cont.}\gdef\MEnote{\doNote{c}{contributor.}}} -% - \let\SPMnote\relax \def\SPM{\doAbre{A}{S. P. M.}\gdef\SPMnote{\doNote{A}{Strategic Project Manager.}}} - \let\VPENGnote\relax \def\VPENG{\doAbre{B}{VP of eng.}\gdef\VPENGnote{\doNote{B}{VP of Engineering.}}} - \let\RENGnote\relax \def\RENG{\doAbre{C}{R. engineer}\gdef\RENGnote{\doNote{C}{Research engineer.}}} - \let\INREnote\relax \def\INRE{\doAbre{D}{I. researcher}\gdef\INREnote{\doNote{D}{Inria researcher.}}} - \let\EPnote\relax \def\EP{\doAbre{E}{E. professor}\gdef\EPnote{\doNote{E}{Emeritus professor.}}} - \let\APnote\relax \def\AP{\doAbre{F}{A. professor}\gdef\APnote{\doNote{F}{Assistant professor.}}} - \let\DMnote\relax \def\DM{\doAbre{G}{D. M.}\gdef\DMnote{\doNote{G}{Department mananger.}}} - %\let\RDENGnote\relax \def\RDENG{\doAbre{H}{R\&D eng.}\gdef\RDENGnote{\doNote{H}{R\&D Engineer.}}} -% - \let\COMPnote\relax \def\COMP{\doAbre{1}{COMP}\gdef\COMPnote{\doNote{1}{Compilation.}}} - \let\SWnote\relax \def\SW{\doAbre{2}{SW}\gdef\SWnote{\doNote{2}{SW development.}}} - \let\SYSnote\relax \def\SYS{\doAbre{3}{SYS}\gdef\SYSnote{\doNote{3}{System design.}}} - \let\VPnote\relax \def\VP{\doAbre{4}{V.P.}\gdef\VPnote{\doNote{4}{Virtual prototyping.}}} - \let\ARCHnote\relax \def\ARCH{\doAbre{5}{ARCH}\gdef\ARCHnote{\doNote{5}{Architecture \& micro-architecture.}}} - \let\MMnote\relax \def\MM{\doAbre{6}{M.M.}\gdef\MMnote{\doNote{6}{Process scheduling \& memory management}}} - \let\AUPAnote\relax \def\AUPA{\doAbre{7}{A.P.}\gdef\AUPAnote{\doNote{7}{Process scheduling \& automatic parallelization.}}} - \noindent\hspace{-0.5cm}\begin{minipage}{\linewidth}\small\begin{tabular}{|c|p{1.4cm}|p{1.7cm}|p{2.3cm}|p{4.4cm}|p{.5cm}|p{4.5cm}|}\hline - & Name & F. name & Position & Fields & \PM & Contribution to the project \\ - }{\end{tabular}\vspace{0.50ex}\\ - \PMnote\COnote\REnote\MEnote - \SPMnote\VPENGnote\RENGnote\INREnote\EPnote\APnote\DMnote - - \\ - \COMPnote\SWnote\SYSnote\VPnote\ARCHnote\MMnote\AUPAnote - - --\\\end{minipage}} - %{\hspace*{1cm}\scriptsize $^{\ast}$ total of PM for the 3 years of the project.}} - -\def\peopletabularentry#1{\hline\hline\multicolumn{7}{|l|}{\textsc{#1}}\\\hline} - -\begin{peopletabular} - -\peopletabularentry{\mds} -\CO & Vaumorin & Emannuel & \SPM & ESL & 20& Task: \TL{1}, 7, \TL{8}\\\hline -\ME & Spasevski & Cyril & CTO & EDA & 6 & Task: 2, 7 \\\hline -\ME & Guntz & St\'ephane & \VPENG & EDA & 6 & Task: 7 \\\hline -\ME & Lucas & Ronan & R\&D Engineer & Codesign & 9 & Task: 3, 7 \\\hline -\ME & Olivier & Garry & R\&D Engineer & \SW & 9 & Task: 3, 7 \\\hline -%\end{peopletabular}\begin{peopletabular} -\peopletabularentry{\upmc} -\RE & Greiner & Alain & professor & SOC \ARCH \VP & 12 & Task: 1, \TL{2}, 3, 6 \\\hline -\ME & Aug\'{e} & Ivan & \AP & HLS \SW SOC HPC & 16 & Task: 1, 3, \TL{3}, 5, 6, 8 \\\hline -%\end{peopletabular}\begin{peopletabular} -\peopletabularentry{\ubs} -\RE & Coussy & Philippe & \mbox{\AP} & SOC HLS \ARCH \VP & 12 & Task: 1, 2, \TL{5}, 8 \\\hline -\ME & Heller & Dominique & \mbox{\RENG} & \COMP HLS \ARCH & 8 & Task: 2, 5, 8 \\\hline -\ME & Chavet & Cyrille & \mbox{\AP} & SOC HLS \ARCH & 4 & Task: 2, 5, 8 \\\hline -%\end{peopletabular}\begin{peopletabular} -\peopletabularentry{\liplong} -\RE & Alias & Christophe & \mbox{\INRE} & \COMP HPC \MM & 13 & Task: 1, 2, \TL{4}, 8 \\\hline -\ME & Feautrier & Paul & \mbox{\EP} & \COMP \AUPA & 12 & Task: 2, 4, 7, 8 \\\hline -%\end{peopletabular}\begin{peopletabular} -\peopletabularentry{\tima} -\RE & P\'etrot & Fr\'ed\'eric& professor & SOC HLS OS \VP \ARCH & 8 & Task: 1, 2, 3, 5, 6 \\\hline -\ME & Muller & Olivier & \mbox{\AP} & SOC \VP HLS & 12 & Task: 2, 3, 5, 6, 8 \\\hline -\ME & Prost-Boucle& Adrien & PhD candidate & SOC HLS & 4 & Task: 5 \\\hline -%\end{peopletabular}\begin{peopletabular} -\peopletabularentry{\inria} -\RE & Charot & François & \mbox{\INRE} & SOC ASIP \ARCH & 15 & Task: 1, 2, 4, 8 \\\hline -\ME & Derrien & Steven & \mbox{\AP} & HLS \COMP\ARCH & 9 & Task: 2, 4, 8\\\hline -%\end{peopletabular}\begin{peopletabular} -\peopletabularentry{\bull} -\RE & Nguyen & Huy-Nam & \DM & HPC \SYS \VP CAD & 9 & Task: 1, 2, \TL{6}, 7, 8 \\\hline -%\end{peopletabular}\begin{peopletabular} -\peopletabularentry{\thales} -\RE & Lemonnier & Fabrice & \DM & SOC ARCH & 7 & Task: 1, \TL{7}, 8 \\\hline -\ME & Brelet & Paul & \mbox{SW\,development} - & \SW & 8 & Task: 7,8 \\\hline -\end{peopletabular} -\caption{\label{involved:people} People that participate to the project.} -\end{figure} Index: r/section-dissemination.tex =================================================================== --- /anr/section-dissemination.tex (revision 386) +++ (revision ) @@ -1,191 +1,0 @@ -\anrdoc{A titre indicatif: 2 pages pour ce chapitre.\\ -Presenter les strategies de valorisation des resultats: -\begin{itemize} -\item la communication scientifique; -\item la communication aupres du grand public (un budget specifique peut être prevu), -\item la valorisation des resultats attendus, -\item les retombees scientifiques, techniques, industrielles, economiques, ... -\item la place du projet dans la strategie industrielle des entreprises partenaires du projet -\item autres retombees (normalisation, information des pouvoirs publics, ...) -\item les echeances et la nature des retombees technico- economiques attendues -\item l'incidence eventuelle sur l'emploi, la creation d'activites nouvelles. -\end{itemize} -Presenter les grandes lignes des modes de protection et d'exploitation des resultats\\ -Pour les projets partenariaux organismes de recherche/entreprises, les -partenaires devront conclure, sous l'egide du coordinateur du projet, un -accord de consortium dans un delai de un an si le projet est retenu pour -financement.\\ -Pour les projets academiques, l'accord de consortium n'est pas obligatoire -mais fortement conseille.} -% -\subsection{Dissemination} - -The COACH project will generate new scientific results in various fields, such as high level synthesis, -hardware/software codesign, virtual prototyping, hardware oriented compilation techniques, -automatic parallelization, etc. These results will be published in relevant International -Conferences, for instance DATE, DAC, or ICCAD. -More generally, the COACH infrastructure and the design flow supported by the COACH -tools and libraries will be promoted by proposing tutorials on FPGA oriented system level synthesis -in various workshops and conferences (DATE, DAC, CODES+ISSS...). -\parlf -Several COACH partners being members of the HiPEAC European Network of Excellence -(High Performance and Embedded Architecture and Compilation), courses will be proposed for the -HiPEAC summer school on Advanced Computer Architecture and Compilation for Embedded Systems. -\parlf -The COACH project will be an open infrastructure, and the COACH tools and libraries will be available via -a WEB server. This server will be maintained by the UPMC/LIP6 laboratory. -On the standardization side, some effort will be made for analysing how the work around IP-XACT -could be donated for the evolution of the IEEE 1685 standard. \mds is board member of -Accellera, TRT, TIMA and LIP6 are members, so we will try to have some influence and at least -communicate on the fact that our solutions will be compatible with the standard. - -\subsection{Industrial exploitation of results} - -The main goal of the COACH project is to help SMEs (Small and Medium Enterprises) and even small design team in larger entities -to enter the world of MPSoC technologies. For small companies or design services, the cost is a primary concern. -Moreover, these companies seldom have in-home expertise in hardware design and VHDL modelling. -As the fabrication costs of an ASIC is generally too high for SMEs, the COACH project focus -on FPGA technologies. Regarding the design tools, the cost of advanced ESL (Electronic System Design) -tools is an issue, and the COACH project will follow the same general policy as the SoCLib platform : - -\begin{itemize} -\item -All software tools supporting the COACH design flow will be available as free software. -All academic partners contributing to the COACH project agreed to distribute the ESL software -tools under the same GPL license. -\item -The SystemC simulation models for the hardware components -used by the SoCLib architectural template will be distributed as free software -under a non-contaminant LGPL license. -\item -The synthesizable VHDL models supporting the neutral architectural template -(corresponding to the SocLib IP cores library: processor core, memory -controllers, ...), will have two modes of dissemination. -%A typical MPSoC contains not only dedicated, synthesized coprocessors. It contains -%also general purpose, reusable components, such as processor cores, memory controllers -%optimised cache controllers, peripheral controllers, or bus controllers. -For non commercial use (i.e. research or education in an academic context, -or feasibility study in an industrial context), the synthesizable VHDL models -will be freely available. -For commercial use, commercial licenses will be negotiated between the owners and the customers. -\item -The proprietary \altera and \xilinx IP core libraries are commercial products -that are not involved by the free software policy, but these libraries will be supported by the -synthesis tools developed in the COACH project. -\item -\mds will propose a commercial version of COACH, integrated into an \mds tool suite and compatible with a standard IP-XACT flow. -This version will integrate some generic features, already available for -production (some of them from a standard \mds pack, some other developed in -COACH). Other COACH features will have to be tailored for the specifics of the -customer framework and will generate service business. -\end{itemize} -% -A large number (\letterOfInterestNb) of SMEs support this general approach -as demonstrated by the "letters of interest" that have been collected during the preparation -of the project and presented in annexe~\ref{lettre-soutien}. - -\subsection{Industrial Interest in COACH} - -\subsubsection*{Partner: \textit{\mds}} -The interest for \mds in this project is multiple. -\begin{itemize} -\item -We will collaborate in experiments for the integration of High Level Synthesis -engines into IP-XACT based flow. This point will be very valuable because more -and more system integrators are using or considering the use of HLS in their development flow -(e.g. Astrium, Airbus, etc.). -\item -\mds has already a leading position in the usage of IP-XACT standard for -managing innovative SoC design methodologies. This project will allow to keep -this competitive advance by anticipating the next generation -platforms hosting multi-cores and programmable logic for coprocessors. -\item -HPC is a topic that was not covered yet by \mds with its customers. Thanks to -this project, \mds will collaborate with BULL on this point and this will open -doors for new customers market. -\item -This project has been set up for maximizing the industrial exploitation of results. -The role of \mds will be to ensure this objective and after the project, we -expect a growing contribution for rising the turnover -(2015: 2 new customers = 100 k\euro, - 2016: 4 new customers = 250 k\euro, - 2017: 5 new customers = 400 k\euro). -These numbers are not high but we tried to keep them realistic. -The return on investment is nevertheless important and we can also expect side -effects of this project on sales with existing customers and prospects -interested in the global \mds solution. -\end{itemize} - -\subsubsection*{Partner: \textit{\bull}} -\noindent -The Bull team participating in COACH is from the Server Design and Development Division, -which is in charge of developing hardware for open servers (e.g.: NovaSacle, Bullion) and -HPC solutions. With this participation, Bull demonstrates its high interest in the outcome of -COACH. Effectively, it is now commonly recognized that the future of HPC will be based -on hybrid architectures in which FPGA will play a major role in the development of configurable -hardware accelerators by providing the best fine grain parallelism. - -\subsubsection*{Partner: \textit{\thales}} -\noindent -\thales has two main reasons to use the COACH platform: -\begin{itemize} - \item The huge increase of the complexity of the systems in particular by their - heterogeneity, raises the issues of design cost and time in the same proportion. The - divisions need a design tool which supports the implementation of the applications from - algorithm description to the executable code on platforms composed of several general - purpose processors and dedicated IPs. - \item The applications are more and more complex and adaptable to the environment which - leads to a mixture of control aspects and data stream computing aspects. A new approach - is necessary to be able to describe this type of application and manage the high level - synthesis of system embedding control and data flow aspects. -\end{itemize} -% -TRT (Thales Research and Technology) has the mission to assess and de-risk the emerging -technologies in its domains of expertise. Specifically in COACH, the studied technology is -a method and associated tools to bridge the gap between application capture at system -level and the implementation on heterogeneous distributed computing architectures. The -main stake for Thales behind this is the future design process that will be applied to its -system teams for computation-intensive sensor applications. In a context -of very unstable market of tools for parallel programming, it is important to experiment -and demonstrate the candidate technologies. -\\ -In its role of internal dissemination, TRT will make the demonstration of the full design -flow within Thales, and will keep available a platform to later evaluate additional -applications coming from the Business Units. -\\ -The COACH platform will be used in the new \thales products in which the algorithms are more -and more dependent of the environment and have to permanently adapt their behavior in -varying environments. The target markets are the critical infrastructures security and -border monitoring. - -\subsubsection*{Industrial supports} - -The following SMEs demonstrate interest to the COACH project (see the "letters of -interest" in annexe~\ref{lettre-soutien}) and will follow the COACH evolution and will -evaluate it: -\letterOfInterest{ALTERA Corporation}{lettres-2011/Altera1.pdf}, -\letterOfInterestPlus{lettres-2011/Altera2.pdf} -\letterOfInterest{FlexRAS Technologies}{lettres-2011/Flexras.pdf}, -\letterOfInterest{INPIXAL}{lettres-2011/Inpixal.jpg}, -\letterOfInterest{CAMKA System}{lettres-2011/Camka.pdf}, -\letterOfInterest{RENESAS Design}{lettres-2011/Renesas-dossier.jpg}, -\letterOfInterest{EADS-ASTRIUM}{lettres-2011/Astrium.pdf}, -\letterOfInterest{CONTINENTAL}{lettres-2011/Continental.pdf}, -\letterOfInterest{TeamCast}{lettres-2011/Teamcast.pdf}, -\letterOfInterest{ALSIM}{lettres-2011/Alsim.pdf}, -\letterOfInterest{NAVTEL Systems}{lettres-2011/Navtel.jpg}. -%\letterOfInterest{ADACSYS}{lettres-2011/Coach_ADACSYS_lettre_interet}, -%\letterOfInterest{ATEME}{lettres-2011/ATEME.pdf}, -%\letterOfInterest{ALSIM Simulateur}{lettres-2011/Alsim.pdf}, -%\letterOfInterest{SILICOMP-AQL}{lettres-2011/itlabs.pdf}, -%\letterOfInterest{ABOUND Logic}{lettres-2011/abound.pdf}, -\letterOfInterestClose - -\subsection{Management of Intellectual Property} -A global consortium agreement will be defined during the first six months of the project. -As already stated, the COACH project has been prepared during one year by a monthly meeting -involving the five academic partners. The general free software policy described in the -previous section has been agreed by academic partners and has been -approved by all industrial participants. This free software policy will -simplify the definition of the consortium agreement. - Index: r/section-etat-de-art.tex =================================================================== --- /anr/section-etat-de-art.tex (revision 386) +++ (revision ) @@ -1,256 +1,0 @@ -% vim:set spell: -% vim:spell spelllang=en: -\anrdoc{\begin{itemize} -\item Presenter un etat de l’art national et international, en dressant l’etat des - connaissances sur le sujet. -\item Faire apparaître d’eventuelles contributions des partenaires de la proposition - de projet a cet etat de l’art. -\item Faire apparaître d’eventuels resultats preliminaires. -\item Inclure les references bibliographiques necessaires en annexe 7.1. -\end{itemize}} - -%Our project covers several critical domains in system design in order -%to achieve high performance computing. Starting from a high level description we aim -%at generating automatically both hardware and software components of the system. - -\subsubsection{High Performance Computing} -\label{soa:hpc} -% Un marché bouffé par les archi GPGPU tel que le FERMI de NvidiaCUDA programming language -The High-Performance Computing (HPC) world is composed of three main families of architectures: -many-core, GPGPU (General Purpose computation on Graphics Unit Processing) and FPGA. -Today, the first two families are dominating the market by taking benefit -of the strength and influence of mass-market leaders (Intel, Nvidia). -%such as Intel for many-core CPU and Nvidia for GPGPU. -In this market, FPGA architectures are emerging and very promising. -By adapting architecture to the software, % (the opposite is done in the others families) -FPGAs architectures enable better performance -(typically an acceleration factor between 10 and 100) -while using smaller size and less energy (and generating less heat). -However, using FPGAs presents significant challenges~\cite{hpc06a}. -First, the operating frequency of an FPGA is low compared to a high-end microprocessor. -Second, % based on Amdahl law, - HPC/FPGA application performance is unusually sensitive -to the implementation quality~\cite{hpc06b}. -% Thus, the performance strongly relies on the detected parallelism. -% (pour résumer les 2 derniers points) -Finally, efficient design methodology are required in order to -hide FPGA complexity and the underlying implantation subtleties to HPC users, -so that they do not have to change their habits and can have equivalent design productivity -than in others families~\cite{hpc07a}. - -%état de l'art FPGA -HPC/FPGA hardware is only now emerging and in early commercial stages, -but these techniques have not yet caught up. -Industrial (Mitrionics~\cite{hpc08}, Gidel~\cite{hpc09}, Convey Computer~\cite{hpc10}) and academic (CHREC) -researches on HPC-FPGA are mainly conducted in the USA. -None of the approaches developed in these researches are fulfilling entirely the -challenges described above. For example, Convey Computer proposes application-specific instruction -set extension of x86 cores in an FPGA accelerator, -but extension generation is not automated and requires hardware design skills. -Mitrionics has an elegant solution based on a compute engine specifically -developed for high-performance execution in FPGAs. Unfortunately, the design flow -is based on a new programming language (mitrionC) implying important designer efforts and poor portability. -% tool relying on operator libraries (XtremeData), -% Parle t-on de l'OPenFPGA consortium, dont le but est : "to accelerate the incorporation of reconfigurable computing technology in high-performance and enterprise applications" ? - -Thus, much effort is required to develop design tools that translate high level -language programs to FPGA configurations. - -\subsubsection{System Synthesis} -\label{soa:system:synthesis} -Today, several solutions for system design are proposed and commercialized. -The existing commercial or free tools do not -cover the whole system synthesis process in a fully automatic way. Moreover, -they are bound to a particular device family and to an IP library. -The most commonly used are provided by \altera and \xilinx to promote their -FPGA devices. These representative tools used to synthesize SoC on FPGA -are introduced below. -\\ -The \xilinx System Generator for DSP~\cite{system-generateur-for-dsp} is a -plug-in to Simulink that enables designers to develop high-performance DSP -systems for \xilinx FPGAs. -Designers can specify and simulate a system using MATLAB and Simulink. The -tool will then automatically generate synthesizable Hardware Description -Language (HDL) code mapped to \xilinx pre-optimized algorithms. -However, this tool targets only signal processing algorithms, \xilinx FPGAs and -cannot handle a complete SoC. Thus, it is not really a system synthesis tool. -\\ -In the opposite, SOPC Builder~\cite{spoc-builder} from \altera and \xilinx -Platform Studio XPS from \xilinx allow to describe a system, to synthesize it, -to program it into a target FPGA and to upload a software application. -Both SOPC Builder and XPS allow designers to select and parameterize components from -an extensive drop-down list of IP cores (I/O core, DSP, processor, bus core, ...) -as well as to incorporate their own IP. Nevertheless, all the previously introduced tools -do not provide any facilities to synthesize coprocessors and to simulate the platform -at a high level (SystemC). -A system designer must provide the synthesizable description of its own IP-cores -interfaces it to the SoC bus. -Design Space Exploration is thus limited and SystemC simulation is not possible -either at transactional or at cycle accurate level. -\\ -In addition, \xilinx System Generator, XPS and SOPC Builder are closed world -since each one imposes their own IPs which are not interchangeable. -Designers can then only generate a synthesized netlist, VHDL/Verilog simulation test -bench and custom software library that reflect the hardware configuration. -\\ -Consequently, a designer developing an embedded system needs to master four -design environments: -\begin{enumerate} - \item a virtual prototyping environment (in SystemC) for system level exploration, - \item an architecture compiler to define the hardware architecture (Verilog/VHDL), - \item one or several third-party HLS tools for coprocessor synthesis (C to RTL), - \item and finally back-end synthesis tools for the bit-stream generation (RTL to bitstream). -\end{enumerate} -Furthermore, mixing these tools requires an important interfacing effort and this makes -the design process very complex and achievable only by designers skilled in many domains. - -\subsubsection{High Level Synthesis} -\label{soa:hls} -High Level Synthesis translates a sequential algorithmic description and a -set of constraints (area, power, frequency, ...) to a micro-architecture at -Register Transfer Level (RTL). -Several academic and commercial tools are today available. The most common -tools are SPARK~\cite{spark04}, GAUT~\cite{gaut08}, UGH~\cite{ugh08} in the -academic world and CATAPULTC~\cite{catapult-c}, PICO~\cite{pico} and -CYNTHETIZER~\cite{cynthetizer} in the commercial world. Despite their -maturity, their usage is restrained by \cite{IEEEDT} \cite{CATRENE} \cite{HLSBOOK}: -\begin{itemize} -\item HLS tools are not integrated into an architecture and system exploration tool. -Thus, a designer who needs to accelerate a software part of the system, must adapt it manually -to the HLS input dialect and perform engineering work to exploit the synthesis result -at the system level, -\item Current HLS tools cannot target control AND data oriented applications, -\item HLS tools take into account mainly a unique constraint while realistic design -is multi-constrained. -The power consumption constraint which is mandatory for embedded systems is not yet -well handled or not handled at all by the HLS tools already available, -\item The parallelism is limited to that present in the initial specification. -To get more parallelism or to reduce the amount of required memory in the SoC, the user -must re-write the algorithmic specification while there are techniques such as polyhedral -transformations that can automate this process. -\item While they support limited loop transformations like loop unrolling and loop -pipelining, current HLS tools do not provide support for design space exploration, either -through automatic loop transformations or for improving the memory mapping, -\item Despite having the same input language (C/C++), they are sensitive to the style in -which the algorithm is written. Consequently, engineering work is required to swap from -a tool to another, -\item They do not respect accurately the frequency constraint when they target an FPGA device. -Their error is about 10 percent. This is annoying when the generated component is integrated -in a SoC since it will slow down the whole system. -\end{itemize} -Regarding these limitations, it is necessary to create a new tool generation reducing the gap -between the specification of an heterogeneous system and its hardware implementation \cite{HLSBOOK} \cite{IEEEDT}. - -\subsubsection{Application Specific Instruction Processors} -\label{soa:asip} -ASIP (Application-Specific Instruction-Set Processor) are programmable -processors in which both the instruction set and the micro architecture have -been tailored to a given application domain or to a -specific application. This specialization usually offers a good compromise -between performance (w.r.t a pure software implementation on an embedded -CPU) and flexibility (w.r.t an application specific hardware co-processor). -In spite of their obvious advantages, using/designing ASIPs remains a -difficult task, since it involves designing both a micro-architecture and a -compiler for this architecture. Besides, to our knowledge, there is still -no available open-source design flow for ASIP design even if such a tool - would be valuable in the -context of a System Level design exploration tool. -\\ -In this context, ASIP design based on Instruction Set Extensions (ISEs) has -received a lot of interest~\cite{NIOS2}, as it makes micro-architecture synthesis -more tractable \footnote{ISEs rely on a template micro-architecture in which -only a small fraction of the architecture has to be specialized}, and help ASIP -designers to focus on compilers, for which there are still many open -problems\cite{ARC08}. -This approach however has a severe weakness, since it also significantly reduces -opportunities for achieving good speedups (most speedups remain between 1.5x and -2.5x), since ISEs performance is generally limited by I/O constraints as -they generally rely on the main CPU register file to access data. -\\ -To cope with this issue, recent approaches~\cite{DAC09,CODES08,TVLSI06} advocate the use of -micro-architectural ISE models in which the coupling between the processor micro-architecture -and the ISE component is tightened up so as to allow the ISE to overcome the register -I/O limitations. However these approaches generally tackle the problem from a compiler/simulation -point of view and do not address the problem of generating synthesizable representations for -these models. -\\ -We therefore strongly believe that there is a need for an open-framework which -would allow researchers and system designers to : -\begin{itemize} -\item Explore the various level of interactions between the original CPU micro-architecture -and its extension (for example through a Domain Specific Language targeted at micro-architecture -specification and synthesis). -\item Retarget the compiler instruction-selection pass -(or prototype new passes) so as to be able to take advantage of this ISEs. -\item Provide a complete System-level Integration for using ASIP as SoC building blocks -(integration with application specific blocks, MPSoc, etc.) -\end{itemize} - -\subsubsection{Automatic Parallelization} -\label{soa:automatic:parallelization} -The problem of compiling sequential programs for parallel computers -has been studied since the advent of the first parallel architectures -in the 1970s. The basic approach consists in applying program transformations -which exhibit or increase the potential parallelism, while guaranteeing -the preservation of the program semantics. Most of these transformations -just reorder the operations of the program; some of them modify its -data structures. Dependences (exact or conservative) are checked to guarantee -the legality of the transformation. -\\ -This has lead to the invention of many loop transformations (loop fusion, -loop splitting, loop skewing, loop interchange, loop unrolling, ...) -which interact in a complicated way. More recently, it has been noticed -that all of these are just changes of basis in the iteration domain of -the program. This has lead to the introduction of the polyhedral model -\cite{FP:96,DRV:2000}, in which the combination of two transformations is -simply a matrix product. -\\ -Since hardware is inherently parallel, finding parallelism in sequential -programs in an important prerequisite for HLS. The large FPGA chips of -today can accommodate much more parallelism than is available in basic blocks. -The polyhedral model is the ideal tool for finding more parallelism in -loops. -\\ -As a side effect, it has been observed that the polyhedral model is a useful -tool for many other optimization, like memory reduction and locality -improvement. It should be noted -that the polyhedral model \emph{stricto sensu} applies only to -very regular programs. Its extension to more general programs is -an active research subject. - -\subsubsection{SoC design flow automation using IP-XACT} -\label{soa:ip-xact} -% EV: Industrial IP integration flows based on IP-XACT standards: \cite{mds1}\\ -% EV: SPIRIT IP-XACT Controlled ESL Design Tool Applied to a Network-on-Chip Platform: \cite{mds2}\\ -% EV: SocKET design flow and Application on industrial use cases: \cite{socketflow}\\ -% IA: http://www.design-reuse.com/articles/19895/ip-xact-xml.html \cite{dandr}\\ -IP-XACT is an XML based open standard defined by the Accellera consortium. -This non-profit organisation provides a unified set of high quality IP-XACT -specifications for documenting IP using meta-data. This meta-data will be -used for configuring, integrating, and verifying IP in advanced SoC design -and interfacing tools using TGI (Tight Generator Interface is a software API) -that can be used to access design meta-data descriptions of complete system designs. -The specification for the schema is tailored to the requirements of the industry, -and focused on enabling technologies for the efficient design of electronic -systems from concept to production. The last IEEE 1685 release of IP-XACT incorporates -both RTL and TLM (transaction level modelling) capabilities. Thus it can be used to -package IP portfolios~\cite{dandr} and describe their assembly in complex hardware architectures.~\cite{mds1}~\cite{mds2} -These description files are the basis for tool interoperability and data exchange -through a common structured data management\cite{socketflow}. Today more than two hundred companies -are members of the consortium and the board is incorporating top actors -(STM, NXP, TI, ARM, FREESCALE, LSI, Mentor, Synopsys and Cadence), ensuring the -wide adoption by industry. Initiatives have already -attempted to extend this standard -to the AMS IPs packaging domain (MEDEA+ Beyond Dreams Project) and to Hardware Dependent -Software layers (MEDEA+ SoftSoc project) and Accellera is reusing these results for -further releases. -\parlf -In IP-XACT the flow automation and data consistency is ensured by generators, which -are program modules that process IP-XACT XML data into something useful -for the design. They are key portable mechanism for encapsulating specialist design -knowledge and enable designers to deploy specialist knowledge in their design. It is -always possible to create generators in order to link several design or analysis tools -around a centric representation of meta-data in IP-XACT. This kind of XML schema for -meta-data management is a good solution for the federation of heterogeneous design domains -(models, tools, languages, methodologies, etc.). - Index: r/section-issues.tex =================================================================== --- /anr/section-issues.tex (revision 386) +++ (revision ) @@ -1,115 +1,0 @@ -\anrdoc{Décrire le contexte économique, social, réglementaire
 dans lequel se -situe le projet en présentant une analyse des enjeux sociaux, économiques, -environnementaux, industriels
 Donner si possible des arguments chiffrés, par -exemple, pertinence et portée du projet par rapport à la demande économique -(analyse du marché, analyse des tendances), analyse de la concurrence, -indicateurs de réduction de coûts, perspectives de marchés (champs -d’application, 
). Indicateurs des gains environnementaux, cycle de vie.} -% -% -\subsubsection*{The electronic market} -Microelectronic components allow integration of complex functions into products, increases -commercial attractiveness of these products and improves their competitiveness. -\cite{rapport-ministere} estimates a 7\% growth of the micro-electronic market until 2015 at least. -Multimedia and communication sectors have taken advantage from microelectronics facilities -thanks to the development of design methodologies and tools for embedded systems. -Unfortunately, the Non Recurring Engineering (NRE) costs involved in the design -and manufacturing of ASICs is very high. -An IC foundry costs several billions of euros and the fabrication of a specific circuit -costs several millions. For example a conservative estimate for a 65nm ASIC project is 10 -millions \$. Consequently, it is more and more unaffordable to design and fabricate ASICs for low and medium -volume markets and the new trend for building the new generation products will be multi processors SoCs and -programmable logic for co-processing. -\\ -According to a market survey (J-M. Chery, CTO ST Microelectronics at European NanoelectronicsForum 2010), -the global growth is 30 billion\$ between 2009-2013 for the multimedia and communication sectors; this is -6 times more than all other domains like security, home automation or health. -The predominance of the multimedia and communication sectors are due to their being predominantly a mass market. -% -\subsubsection*{FPGAs and Embedded Systems} -Today, FPGAs become important in the computational domain that was originally dominated -by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed -on a per-application basis. For many applications, FPGAs offer significant performance benefits over -microprocessors implementation. There is still a performance degradation of one order -of magnitude versus an equivalent ASIC implementations, but low cost -(500 euros to 10K euros), fast time-to-market and flexibility of FPGAs make them an attractive -choice for low-to-medium volume applications. -Since their introduction in the mid eighties, FPGAs evolved from a simple, -low-capacity gate array to devices (\altera STRATIX III, \xilinx Virtex6) that -provide a mix of coarse-grained data path units, memory blocks, microprocessor cores, -on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement -complex systems like multi-processors platform with application dedicated coprocessors. -Table~\ref{fpga_market} shows the estimation of the FPGA worldwide market in the next years in -various application domains. The ``high end'' lines concern only FPGA with high logic -capacity for complex system implementations. -This market is in significant expansion and is estimated to 914\,M\$ in 2012. -%The HPC market size is estimated today by FPGA providers at 214\,M\$. -%Using FPGA limits the NRE costs to the design cost. -%This boosts the developpment of automatic design tools and methodologies. -% -\begin{table}\leavevmode\center -\begin{small}\begin{tabular}{|l|l|l|l|}\hline -Segment & 2010 & 2011 & 2012 \\\hline\hline -Communications & 1,867 & 1,946 & 2,096 \\ -High end & 467 & 511 & 550 \\\hline -Consumer & 550 & 592 & 672 \\ -High end & 53 & 62 & 75 \\\hline -Automotive & 243 & 286 & 358 \\ -High end & - & - & - \\\hline -Industrial & 1,102 & 1,228 & 1,406 \\ -High end & 177 & 188 & 207 \\\hline -Military/Aeronautic & 566 & 636 & 717 \\ -High end & 56 & 65 & 82 \\\hline\hline -Total FPGA/PLD & 4,659 & 5,015 & 5,583 \\ -Total High-End FPGA & 753 & 826 & 914 \\\hline -\end{tabular}\end{small} -\caption{\label{fpga_market} Gartner estimation of worldwide FPGA/PLD consumption (Millions \$)} -\end{table} -\subsubsection*{FPGAs and High Performance Computing} -Today, several companies (Atipa, blue-arc, Bull, Chelsio, Convey, CRAY, DataDirect, DELL, hp, -Wild Systems, IBM, Intel, Microsoft, Myricom, NEC, nvidia etc) are making systems where demand -for very high performance (HPC) primes over other requirements. They tend to use the highest -performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative -architectures and algorithms. These companies show up in different "traditional" applications and market -segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC -emulation and prototyping, military/aeronautic etc. The HPC market size is estimated today by FPGA providers -at 214\,M\$. -This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion -of FPGA-based solutions is limited by the lack of design automation. -% -\subsubsection*{Evolution of architectures} -Nowadays processors mixing core and programmable matrix are available on the market (eg. Intel ATOM E600C). -Donald Newell, AMD technical manager, envisions that such circuits will be at the heart of most of the electronic -products (eg. PDAs and nomad items) and even personal computers. -To take benefit of such architectures, developping and deploying application will require innovative -codesign methods and tools. - -% -\subsubsection*{COACH's contribution to this evolution} -Nowadays, there are no commercial or academic tools covering the whole design flow -from the system level specification to the bitstream generation, either for embedded system design -or for HPC. -\begin{center}\begin{minipage}{.9\linewidth}\textit{ -The aim of the COACH project is to integrate all these design steps into a single design framework -and to allow \textbf{pure software} developers to design embedded systems. -}\end{minipage}\end{center} -% -The COACH project proposes an open-source framework for mapping multi-tasks software applications -on Field Programmable Gate Array circuits (FPGA). -Its aim is to propose solutions to the societal/economical challenges by -providing industrials using FPGAs and in particular SMEs novel design -capabilities enabling them to increase their design productivity with design -exploration and synthesis methods that are placed on top of the state-of-the-art -methods. -We believe that the combination of a design environment dedicated to software developers -and FPGA targets, -will allow small and even very small companies to propose embedded system and accelerating solutions -for standard software applications with attractive and competitive prices. -This new market may explode in the same way as the micro-computer market in the eighties, -whose success was due to the low cost of the first micro-processors (compared to main frames) -and the advent of high level programming languages which allowed a high number of programmers -to launch start-ups in software engineering. -\\ -So this may increase the total -number of engineers working in this domain: today in France the total is only 26,000 of which -16,000 are in big companies \cite{rapport-ministere}. Index: r/section-objectif.tex =================================================================== --- /anr/section-objectif.tex (revision 386) +++ (revision ) @@ -1,100 +1,0 @@ -\anrdoc{\begin{itemize} -\item Decrire les objectifs du projet et detailler les verrous scientifiques et - techniques a lever par la realisation du projet. Insister sur le caractÚre - ambitieux et/ou novateur de la proposition. -\item Decrire eventuellement le ou les produits finaux developpes, presenter les - resultats escomptes en proposant si possible des critÚres de reussite et - d’evaluation adaptes au type de projet, permettant d’evaluer les resultats en - fin de projet. -\end{itemize}} - -% les objectifs scientifiques/techniques du projet. -The design steps are presented in figure~\ref{coach-flow}. -The end-user input is -either an HPC application (an application running on a PC that must be accelerated), -or an embedded application (a standalone application), -or a sub-system application of a larger design. -The figure shows that the design flow of embedded and sub-system applications does not differ -except in the generation step and that the design flow of HPC application just adds a -preliminary step. -\begin{figure}[hbtp]\leavevmode\center - \includegraphics[width=1.0\linewidth]{flow2} - \caption{\label{coach-flow} COACH design flow} -\end{figure} -\begin{description} -\item[HPC setup:] During this step, the user splits the application into 2 parts: the host application -which remains on the PC and the SoC application which is mapped on the FPGA. -COACH will provide a complete simulation model of the whole system (PC+communication+FPGA-SoC) -which will allow performance evaluation. -\item[SoC design:] In this phase, -COACH will allow the user to obtain virtual prototypes for the SoC at different abstraction levels. -The user input will consist of a process network describing the coarse grain parallelism -of the application, an instance of an architectural template -and a mapping of processes on the architectural template components. -COACH will offer different targets to map the processes: -software (the process runs as a software task on a SoC processor), -ASIP (the process runs as a software task on a SoC processor enhanced with dedicated instructions), -and hardware (the process is implemented as a synthesized hardware coprocessor). -\item[Generation:] -Once the SoC architecture is validated through performances analysis, -COACH generates its bitstream in the case of HPC or embedded application, -or its IP-XACT description for its integration in the case of a sub-system application. -Both descriptions contain the hardware architecture and the application software. -Furthermore in the HPC case, an executable containing the host application is -also generated and the user will be able to launch the application by loading -the bitstream on an FPGA and running the executable on a PC. -\end{description} -% Detailler les verrous scientifiques et techniques a lever par la realisation du projet. -Hardware/Software co-design is a very complex task. To simplify it, COACH will address the -following scientific and technological barriers: -\begin{description} -\item[\textit{Design Space Exploration by Virtual Prototyping}]: - The COACH environment will allow to easily map a parallel application (formally described as - an abstract network of process and communication channels). - COACH will permit the system designer to explore the design space, and to define the best - hardware/software partitioning of the application. -\item[\textit{Integration of system level modeling and HLS tools}]: - COACH will support the automated generation of hardware accelerators when required - by using High-Level Synthesis (HLS) tools. These HLS tools will be - fully integrated into a complete system-level design environment. - Moreover, COACH will support both data and control dominated applications, - and the HLS tools of COACH will support a common language and coding style - to avoid re-engineering by the designer. - COACH will provide a tool which will automatically explore the coprocessor micro-architectural design space. -\item[\textit{High-level code transformation}]: - COACH will allow optimization of the memory usage, enhancing the parallelism through - loop transformations and parallelization. The challenge is to identify the coarse - grained parallelism and to generate, - from a sequential algorithm, an application containing multiple communicating processes. - COACH will adapt techniques which were developed in the 1990 for - the construction of distributed programs. However, in the context of HLS, there are - several original problems to be solved, related to the FIFO communication channels and to - memory optimization. - COACH will support code transformation by providing a source to source C2C tool. -\item[\textit{Unified Hardware/Software communication middleware}]: - COACH will rely on the SoCLib experience to implement an unified hardware/software communication - infrastructure and communication APIs (Application Programming Interface), to support - communications between software tasks running on embedded processors and dedicated - hardware coprocessors. The main issue here is to support easy migration - from a software implementation to an hardware implementation. -\item[\textit{Processor customization}]: - ASIP (Application Specific Instruction Processor) design will be addressed by the COACH project. - COACH will allow system designers to explore the various level of interactions between - the original CPU micro-architecture and its extension. It will also allow to retarget - the compiler instruction-selection pass. Finally, COACH will integrate ASIP synthesis - in a complete System-level design framework. -\end{description} -%Presenter les resultats escomptes en proposant si possible des criteres de reussite -%et d'evaluation adaptes au type de projet, permettant d'evaluer les resultats en -%fin de projet. -The main result is the framework. It is composed concretely of: -a communication middleware for HPC, -5 HAS tools (control dominated HLS, data dominated HLS, Coarse grained HLS, -Memory optimization HLS and ASIP), -3 architectural templates that are synthesizable and that can be prototyped, -one design space exploration tool, -1 operating systems (DNA/OS). -\\ -The framework functionalities will be demonstrated with the demonstrators -(see task-7 page~\pageref{task-demonstrator}) and the tutorial example (see task-8 -page~\pageref{subtask-tutorial}). Index: r/section-position.tex =================================================================== --- /anr/section-position.tex (revision 386) +++ (revision ) @@ -1,207 +1,0 @@ -\anrdoc{Preciser:\begin{itemize} -\item positionnement du projet par rapport au contexte developpe precedemment : - vis- a-vis des projets et recherches concurrents, complementaires ou - anterieurs, des brevets et standards... -\item indiquer si le projet s'inscrit dans la continuite de projet(s) anterieurs - deja finances par l'ANR. Dans ce cas, presenter brievement les resultats acquis, -\item positionnement du projet par rapport aux axes thematiques de l'appel a projets, -\item positionnement du projet aux niveaux europeen et international. -\end{itemize}} - -% Relevance of the proposal -%The COACH proposal addresses directly the \emph{Embedded Systems} item of -%the ARPEGE program. - -%PC => IA et ALain -%J'aui déplacé le pargraphe ci dessous en conclusion de la section précédente 2.1 - -%It aims to propose solutions to the societal/economical challenges by -%providing SMEs novel design capabilities enabling them to increase their -%design productivity with design exploration and synthesis methods that are placed on top -%of the state-of-the-art methods. -%This project proposes an open-source framework for mapping multi-tasks software applications -%on Field Programmable Gate Array circuits (FPGA). -%%% -\subsubsection*{Positioning in regards with the economical and social context} -COACH will contribute to build an open design and run-time -environment, including communication middleware and tools to support -developers in the production of embedded software, through all phases of the software life cycle, -from requirements analysis down to deployment and maintenance. -More specifically, COACH focuses on: -\begin{itemize} -\item High level methods and concepts (esp. eequirements and architectural level) for system -design, development and integration, addressing complexity aspects and modularity. -\item Open and modular design environments, enabling flexibility and extensibility by -means of new or sector-specific tools and ensuring consistency and traceability along the -development life cycle. -\item Light/agile methodologies and adaptive workflow providing a dynamic and adaptive -environment, suitable for co-operative and distributed development. -\item Integration of the solutions and engines being developed into a state of the art SoC and system -design flow, using the IP-XACT IEEE 1685 specification. -\end{itemize} -The COACH results will contribute to strengthen Europe's competitive position by developing -technologies and methodologies for product design, focusing (in compliance with the -%scope of the above program) on technologies, engineering methodologies, novel tools, -%methods which facilitate resource use efficiency. The approaches and tools to be developed -%in COACH will enable new and emerging information technologies for the development, -%methods which facilitate resource use efficiency. The COACH approaches and tools -scope of the above program) on technologies, engineering methodologies, novel tools -which facilitate resource use efficiency. The COACH approaches and tools -will enable new and emerging information technologies for the development, -manufacturing and integration of devices and related software into end-products. -%%% -\subsubsection*{Positioning and continuity with other projects} -The COACH project will benefit from a number of previous recent projects: -\begin{description} - \item[SOCLIB] - The SoCLib ANR platform (2007-2009) is an open infrastructure - that supports system level virtual prototyping of shared memory, multi-processors - architectures, and provides tools to map multi-tasks software application on these - architectures, for reliable performance evaluation. - The core of this platform is a library of SystemC simulation models for - general purpose IP cores. - It provides also embedded operating systems and software/hardware - communication middleware. - \item[ROMA] The ROMA ANR project (2007-2010) \cite{roma,RAFFIN:2010:INRIA-00539874:1} - involving IRISA (CAIRN team), LIRMM, CEA List, THOMSON France R\&D, - proposes to develop a reconfigurable processor, exhibiting high - silicon density and power efficiency, able to adapt its computing - structure to computation patterns that can be faster or more - power efficient. %The ROMA project study a pipeline of - %evolved low-power coarse grain reconfigurable operators to avoid - %traditional overhead, in reconfigurable devices, related to the - %interconnection network. - The project will borrow from the ROMA - ANR project and the ongoing joint INRIA-STMicro - Nano2012 project to adapt existing pattern extraction algorithms - and datapath merging techniques to ASIP synthesis. -% and datapath merging techniques to the synthesis of customized -% ASIP processors. - \item[TSAR] - The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and \upmc targets the design of a -% The TSAR MEDEA+ project (2008-2010) targets the design of a - scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib - platform for virtual prototyping. COACH will benefit from the synthesizable VHDL - models developed in the framework of TSAR (MIPS32 processor core, and RING interconnect). - \item[BioWic] - On the HPC application side, we also hope to benefit from the experience in - hardware acceleration of bioinformatic algorithms/workfows gathered by the - CAIRN group (ANR BioWic project 2009-2011), so as to - be able to validate the framework on real-life HPC applications. - - \item[SoCket] - The design flow defined in this project targets the design of critical embedded systems. - It covers important steps as system architecture exploration, and the definition of virtual - prototypes at different levels of abstraction to support early embedded software development, - verification of hardware blocks, and preparation of certification activities. - COACH solutions and engines will be specified to be integrated into this standard flow. - MDS, Thales TRT, TIMA are already collaborating in this project. - - \item[HOSPI] - The objective of this project (with TIMA and MDS) was to define innovative methods, and implement the associated tools, to ease - the mapping of data-streaming applications on heterogeneous platforms. COACH will use the abstracted description - format based on IP-XACT for hardware platforms and the results concerning the integration of code generators into a standard design flow. - - \item[SoftSoC] - TIMA and MDS are involved in this project which aims at the - definition and generation of Hardware Dependent Software layers of a - system. - Crucial extensions of the IP-XACT standard will be reused from this - project, as well as code generation techniques based on them. - -\end{description} -%%% -The partners involved in the COACH project have a well established expertise -in the following domains: -\begin{itemize} - \item - In the field of High Level Synthesis (HLS), the project - leverages on know-how acquired over the last 15 years with the GAUT~\cite{gaut08} project - developed by the \ubs laboratory, and with the UGH~\cite{ugh08} project developed - by the \upmc and \tima laboratories. - \item - Regarding system level architecture, the project is based on the know-how - acquired by \upmc and \tima in the framework of various projects - in the field of communication architectures for shared memory multi-processors systems - (COSY~\cite{cosy}, DISYDENT~\cite{disydent05} or DSPIN~\cite{dspin08} of MEDEA-MESA). - As an example, the DSPIN project is now used in the TSAR project. - \item - Regarding Application Specific Instruction Processor (ASIP) design, the - CAIRN group at INRIA Rennes -- Bretagne Atlantique benefits from several years of - expertise in the domain of retargetable compiler - (Armor/Calife~\cite{CODES99} since 1996, and the Gecos - compilers~\cite{ASAP05} since 2002). - \item - In the field of compilers, the \lip Compsys group was founded in 2002 - by several senior researchers with experience in - high performance computing and automatic parallelization. They have been - among the initiators of the polyhedral model, a theory which serve to - unify many parallelism detection and exploitation techniques for regular - programs. It is expected that the techniques developed by \lip for - parallelism detection, scheduling \cite{Feau:92aa,Feau:92bb}, - process construction \cite{Feau:96} and memory management \cite{bee} - will be very useful as a front-end for HLS tools. - \item - Regarding industrial flow integration \mds will bring its strong expertise - in IEEE 1685 (IP-XACT) standard. The \mds team is involved and contributes actively - to it since 2003 and the Magillem tool suite is used for its validation. Magillem is used in - industrial production flows of ST, NXP, TI, Qualcomm, and system integrators like Thales, - Astrium, Thomson, etc. This guarantees a strong alignement on customers needs and enhanced results exploitation. - -\end{itemize} -%%% -\subsubsection*{Relevance to the call axis} -This project answer to the global statement of the call "INGENIERIE NUMERIQUE ET SECURITE (INS)" by proposing -methods and tools for the design of application to be run on platforms of the next generation. -Improvements can be expected for productivity, -time-to-market (automation and code generation) and reliability (management of high level specifications down to implementation). -In this call, the COACH project totally fulfills the objectives of the axis 2 "METHODES, -OUTILS ET TECHNOLOGIES POUR LES SYSTEMES EMBARQUES". -COACH will address new embedded systems architectures by allowing the design of -Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design -constraints and objectives (real-time, low-power). It will permit designing complex SoC -based on IP cores (memory, peripherals...), -running Embedded Software, as well as an Operating System with associated middleware and -API and using automatically generated hardware accelerators. It will also permit to use -efficiently different dynamic system management techniques and re-configuration mechanisms. -The results will be tailored in order to be integrated in standard design flow of critical systems. -\\ -COACH will address High-Performance Computing (HPC) by helping designers to accelerate an -application running on a PC. -By providing tools that translate high level language programs to FPGA -configurations, COACH will allow to easily migrate critical parts into an FPGA plugged to the -PC bus (through a communication link like PCI/X). -\parlf -The COACH project has been also shaped to answer to the axis 5 "USAGES". -COACH will address robotic and control applications by -allowing to design complex systems based on MPSoC architecture. -Like in the consumer electronics domain, future control applications -will employ more and more SoC for safety and security applications. -Application domains for such systems are for example automotive -or avionics domains (e.g. collision-detection, intelligent navigation...). -Manufacturing technology will also increasingly need high-end vision analysis and high-speed -robot control. -% -The results of the COACH project will help users to build cryptographic secure systems implemented in -in a combination of hardware and software in an effective way, substantially enhancing the -productivity of the field, improving the -quality and reducing the design time and the cost of synthesised cryptographic devices. -% -COACH will contribute to enhance the safety in design of critical system for two main reasons: -\begin{itemize} - \item by providing a way to automate the mapping of application onto MPSoC - architecture; code generators of the tool chain will be subject to - certification. - \item by relaying on design flow defined by SoCKET, which is dedicated to - safety of critical systems, COACH will benefit from features related to - requirements traceability. -\end{itemize} -% -\subsubsection*{European and international positioning} -% -Finally, it is worth noting that this project covers priorities defined by the commission -experts in the field of Information Technologies Society (IST) for Embedded -Systems: \textit{ $<<$Concepts, methods and tools for designing systems dealing with systems complexity -and allowing to apply efficiently applications and various products on embedded platforms, -considering resources constraints (delays, power, memory, etc.), security and quality -services$>>$}. Index: r/section-project-description.tex =================================================================== --- /anr/section-project-description.tex (revision 386) +++ (revision ) @@ -1,162 +1,0 @@ -\anrdoc{% -Presentez le programme scientifique et justifiez la decomposition en taches du -programme de travail en coherence avec les objectifs poursuivis.\\ -Utilisez un diagramme pour presenter les liens entre les differentes taches (organigramme technique)\\ -Les taches representent les grandes phases du projet. Elles sont en nombre -limite.\\ -Le cas echeant (programmes exigeant la pluridisciplinarite), demontrer -l'articulation entre les disciplines scientifiques.\\ -N'oubliez pas les activites et actions correspondant à la dissemination et à la valorisation.} - - -\begin{figure}[h!]\leavevmode\center -\includegraphics[width=.7\linewidth]{architecture-csg} -\caption{\label{archi-csg} Software architecture for digital system generation} -%\end{figure}\begin{figure}\leavevmode\center -%\mbox{}\vspace*{1ex}\\ -\includegraphics[width=1.0\linewidth]{architecture-hls} -\caption{\label{archi-hls} Software architecture of HAS (hardware Accelerator Synthesis)} -%\end{figure}\begin{figure}\leavevmode\center -%\mbox{}\vspace*{1ex}\\ -\includegraphics[width=.65\linewidth]{architecture-hpc} -\caption{\label{archi-hpc} Performance analysis of a HPC partitioning} -\end{figure} -% -Figures~\ref{archi-csg}, \ref{archi-hls} and \ref{archi-hpc} -summarize the software architecture of the COACH framework we will develop. -In figures, the dotted boxes are the softwares or formats that COACH -has to provide and to support. -\parlf -For the system generation presented in figure~\ref{archi-csg}, the conductor -is the tool \verb!CSG! (COACH System Generator). Its inputs are a process -network describing the target application and the synthesis parameters. -The main parameters are the target hardware architectural template -with its instantiation parameters, the hardware/software mapping of the -tasks, the FPGA device and design constraints. -\verb+CSG+ thus requires an architectural template library, an operating system -library, two system hardware component (CPU, memories, BUS...) libraries -(one for synthesis, one for simulation). -For generating the coprocessor of a task mapped as hardware, \verb+CSG+ -controls the \verb!HAS! (Hardware Accelerator Synthesis) tools described below. -From these inputs \verb!CSG! can generate the entire system (both software and -hardware) either as an IP under IP-XACT to integrate the SoC in larger -design or -as a SystemC simulator (cycle accurate and/or TLM) to prototype and explore quickly the -design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and -launch the \xilinx or \altera RTL synthesis tools.} directly downloadable on the -FPGA device\footnote{Additional partial bitstreams are generated in case of - dynamic partial reconfiguration}. - \\ - Furthermore the architecture template and hardware component libraries will be described - under the IP-XACT specification to facilitate the configuration of \verb+CSG+ to other - architecture or the enhancement of existing template with IP. -\parlf -The software architecture for \verb!HAS! is presented in figure~\ref{archi-hls}. -The input is a single task of the process network. The \verb!HAS! tools do not work -directly on the C++ task description but on an internal format called -\xcoach generated by a plugin into the GNU C compiler (GCC). -This will allow on the one hand to insure that all the tools will -accept the same C++ description and on the other hand make possible -their chaining. The front-end tools read an \xcoach description and generate -a new \xcoach description that exhibits more parallelism or implement -specific instructions for ASIP. The back-end tools read an \xcoach -description and generate an \xcoachplus description. This is an \xcoach -description annotated with hardware information (scheduling, binding) required by -the VHDL and systemC drivers. -Furthermore, the back-end tools use a macro-cell library (functional and memory -unit). -\parlf -\label{HPC:howto}% -In addition to digital system design, HPC requires a supplementary -partitioning step presented in figure~\ref{archi-hpc}. The designer -splits the initial application (tag 1) into two parts: one still on the PC and the -other running in a FPGA plugged on the PCI/X PC bus. The two parts exchange data -through communication primitives (tag 2) implemented in a library. -To evaluate the relevance of the partitioning, the designer can build a -simulator. Once the partitioning is validated, the design of the FPGA part -is done through \verb!CSG! (figure~\ref{archi-csg}). -\parlf -The project is split into 8 tasks. They are described -in short below and in detail in section \ref{task-description}. -\begin{description} -\item[Task-1: \textit{Project management}] - This task relates to the monitoring of the COACH project. -\item[Task-2: \textit{\Backbone}] This task tackles the fundamental points of the - project such as the definition of the COACH inputs and outputs, - the internal formats (i.e. \xcoach and \xcoachplus) and their associated tools, - the architectural templates and the design flow. -\item[Task-3: \textit{System generation}] This task addresses the prototyping and - the generation of digital system. Apart from \verb!HAS! that belongs to task 3 - and 4, its components are those presented in figure~\ref{archi-csg} - (e.g. \verb!CSG!, operating systems). -\item[Task-4: \textit{HAS front-end}] This task mainly focusses on four functionalities: - optimization of the memory usage, parallelism enhancement through loop - transformations, coarse grain parallelization and ASIP generation. -\item[Task-5: \textit{HAS back-end}] This task groups two functionalities: - High-Level Synthesis of data dominated description and HLS of control - dominated description. - This task contains also the development of a frequency adapter - that will allow the coprocessors to meet processor and bus - frequency constraints. -\item[Task-6: \textit{PC/FPGA communication middleware}] - This task pools the features dedicated to HPC. These are mainly the - validation of the partitioning (see figure~\ref{archi-hpc}), the system drivers for - both PC and FPGA-SoC sides, the hardware communication components and - the support for dynamic partial reconfiguration. -\item[Task-7: \textit{Industrial demonstrators}] - This task groups the demonstrators of the COACH project. - Most of them are industrial applications that will be developed within - the COACH framework. - Others consist in integrating the COACH framework into - industrial proprietary design tools. -\item[Task 8: \textit{Dissemination}] - This task concerns the diffusion of the project results. - It mainly consists of the production of 4 COACH releases (\verb!T0+12!, \verb!T0+18!, - \verb!T0+24! and \verb!T0+36!), the publication of a tutorial and user manuals on a WEB site, the publication - of research papers in international journals and conferences and the organization of workshops and tutorials in - international conferences. -\end{description} -% -\begin{figure}\leavevmode\center -%\includegraphics[width=.4\linewidth]{dependence-task} -\includegraphics[width=0.50\linewidth]{dependence-task-h} -\caption{\label{dependence-task}Task dependencies} -\end{figure} -Figure~\ref{dependence-task} presents the tasks dependencies. -"$T_N \longrightarrow T_M$" means that $T_N$ impacts the $T_M$. -The more bold the arrow, the more important is the impact. -The graph shows: -\begin{itemize} -\item Even though $T4$ and $T5$ functionalities are complementary, -their developments are independent (thanks to the \xcoach internal format). -\item $T3$ slightly depends on $T4$ and $T5$. Indeed, $T3$ may work -without $T4$ and $T5$ if targeted digital systems do not include hardware -accelerators. -\item $T3$ strongly impacts $T6$ but $T3$ does not depend at all on -$T6$. Hence demonstrators ($T7$) of embedded system would not be impacted if -$T6$ would fail. -\item $T2$ drives all the tasks ($T3$, $T4$, $T5$, $T6$) and is at the heart of -the COACH project. -\item The demonstrators developed in $T7$, of course strongly depend on the achievements -of the previous tasks ($T2$, $T3$, $T4$, $T5$, $T6$). -\item $T8$ and $T1$ depend on and impact all the other tasks. -\end{itemize} -%This organisation offers enough robustness to insure the success of the -%project, the only critical task in this chart being $T2$. -%%However, the partners met 12 times (a one-day meeting per month) during the last year. -%%Ten meeting were dedicated to preliminary technical discussions, including a tentative specification -%%of {\tt xcoach}. The other meetings were dedicated to the preparation of the present proposal. -%However, the partners had 10 one-day meetings where a preliminary draft of the -%\xcoach format was defined. This makes this task less critical. -This project has been shaped with this chart in order to minimize the technical -risk: the task $T2$ handles the major technical issues to be solved and as it is -planned at the beginning of the project we will be able to react fast and take -decisions for possible workaround and enable the continuation of the work with -other tasks. -\label{xcoach-problem} -Nevertheless, we are confident because in preparation to this project, -academic partners are already working close together and know well each other's -technologies, and also a lot of face to face meeting are planned at the -beginning of the project in task $T2$ in order to define the \xcoach format which is -the corner stone of the COACH platform. - Index: r/section-project-management.tex =================================================================== --- /anr/section-project-management.tex (revision 386) +++ (revision ) @@ -1,80 +1,0 @@ -\anrdoc{Preciser les aspects organisationnels du projet et les modalites de -coordination (si possible individualisation d’une tache de coordination).} - -\begin{description} -\item[Project management structure] -Each task is assigned to a Task Leader. -The Task Leaders assist the project leader in the technical organization, effort -management, and progress reporting. -A steering committee is composed by task leaders and the project leader. -The steering committee has a monthly conference call and is in charge of conflict -management if necessary. -Each task leader has to report on the main high-lights, major -opportunities and problems according to the work-plan. -The redaction of the 6-month reports is the responsibility of the steering committee. -Therefore, each Partner has the responsibility to monthly inform the task Leaders of the -current development of the \ST he is in charge of. -COACH will be organized in 8 tasks whose interactions are presented in -Figure~\ref{dependence-task}. - -\item[Scientific and Technical Reports] -For every yearly review, the task leader will provide a written progress report -for each deliverable to the coordinator for integration in the contractual reports. - -\item[Management of knowledge, Intellectual Property Right (IPR) and Results Exploitation] -%The partners will have to work under eventual NDA constraints. -%Prior Intellectual Property remains property of the concerned partners. -%The exploitation of the results obtained in the project and by each partner involved in the consortium will -%follow the rules written in the articles of the Consortium Agreement accepted and signed by -%each partner at most 6 months after the project kick-off. -%To manage the exploitation and dissemination plan within the project, six -%monthly meetings will analyze the intentions from the consortium (patent, publication...). -The partners will sign and accept the Consortium Agreement at most 6 months -after the project kick-off. It will -1) eventually set NDA constraints on industrial demonstrators, -2) fix the intellectual properties of both prior and created intellectual properties, -3) define the rules of exploitation of the results obtained in the project. -\\ -To manage the exploitation and dissemination plan within the project, six -monthly meetings will analyze the intentions from the consortium (patent, publication...). - -\item[Management Tools] -In order to permit a good management, before the kick-off meeting, -each partner will have to identify (name, address, phone, fax and e-mail): -\begin{itemize} - \item the financial and administrative contact person, - \item the scientific and technical contact person, - \item all participants to the project. -\end{itemize} -A complete and detailed list will be communicated to each partner and to -the public Authority. The partners will construct mailing lists for -day-to-day communication. -\parlf -The first task will be the redaction of a Consortium Agreement, -dealing mainly with all aspects of the relations -between partners, including legal aspects, property rights and further -exploitation of the results. This document will be submitted to the -partner's financial and legal departments, and will define the management -rules (decision level, reporting systems, red flag cases). -A first draft of this document will be submitted to each partner -during the kick-off meeting. - -\item[Project follow-ups] -The basic communication between single project partners will be carried out by -means of an Information System (web site), which will be developed and -introduced at the very beginning of the project implementation. -All scientific and administrative data related to the project will be collected and -treated within a specific e-management plate-form accessible directly by the project web -site by an individual login and pass-word. -The web site will have a few levels of accessibility starting with completely free access, -open to broad public up to internal materials available only for members of the consortium -for the e-management area. -This communication tools will permit to perform all the reports and to follow as well as -possible all the tasks. - -\item[Project monitoring] -For this project format and size, a 12 months review by ANR, based on a yearly progress -report incorporating milestones reports and deliverables, seems optimum. -The internal consortium meetings will be every six months, including a kick-off meeting at the -start of the project, in our eyes the most important of all, as it phases the partners for the start of the project. -\end{description} Index: r/section-project-task-schedule.tex =================================================================== --- /anr/section-project-task-schedule.tex (revision 386) +++ (revision ) @@ -1,149 +1,0 @@ -\anrdoc{\begin{itemize} -\item Presenter sous forme graphique un echeancier des differentes taches -et leurs dependances (diagramme de Gantt par exemple). -\item Presenter un tableau synthetique de l'ensemble des livrables du -projet (numero de tache, date, intitule, responsable). -\item Preciser de facon synthetique les jalons scientifiques et/ou -techniques, les principaux points de rendez-vous, les points bloquants ou -aleas qui risquent de remettre en cause l'aboutissement du projet ainsi que -les reunions de projet prevues.\end{itemize}} - -\definecolor{gtcBoxHeavy}{rgb}{0.10,0.10,0.90} -\definecolor{gtcBoxLight}{rgb}{0.9,0.90,0.99} -\definecolor{gtcTaskBG0} {rgb}{0.99,0.90,0.7} -\definecolor{gtcTaskBG1} {rgb}{0.90,0.99,0.7} -\definecolor{gtcMilestone}{rgb}{0.9,0.4,0.4} -\immediate\write\ganttdata{ML=6 ML=12 ML=18 ML=27} -%\def\ganttlabelstyle#1{\begin{small}#1\end{small}} -\def\ganttlabelstyle#1{\begin{small}\hyperlink{#1}{#1}\end{small}} -\def\gantttitlestyle#1{\begin{scriptsize}\textit{#1}\end{scriptsize}} - -\begin{figure}\leavevmode\center -\hypersetup{ - %backref=true, - %pagebackref=true, - %hyperindex=true, - colorlinks=true, %colorise les liens - breaklinks=true, %permet le retour à la ligne dans les lien - urlcolor= blue, %couleur des hyperliens - linkcolor= black %couleur des liens internes -} -\hspace*{-.6cm} -\input{gantt.tex} -\caption{\label{gantt}Gantt diagram of deliverables} -\end{figure} - -%\begin{figure}\leavevmode\center -%\hspace*{-.4cm}%\vspace{-1.5cm} -%\input{gantt1.tex} -%\caption{\label{gantt1}Gantt diagram of deliverables (task-1 to task-6)} -%\end{figure} -% -%\begin{figure}\leavevmode\center -%\hspace*{-.4cm}%\vspace{-1.5cm} -%\input{gantt2.tex} -%\caption{\label{gantt2}Gantt diagram of deliverables (task-7 and task-8)} -%\end{figure} - -Figure~\ref{gantt} presents the Gantt diagram of the project. -%The figures~\ref{gantt1}~\&~\ref{gantt2} present the Gantt diagram of the project. -Before the final release (T0+36), there are 4 milestones (red lines on the figures) at -$T0+6$, $T0+12$, $T0+18$ and $T0+27$ that are rendez-vous points of the precedent -deliverables. -\begin{description} - \item[Milestone 1 ($T0+6$)] - Specification of COACH inputs, of the \xcoach format and of - the demonstatrors as a reference software. - \item[Milestone 2 ($T0+12$)] - The first COACH release. At this step the demonstrators are - written in the COACH input format. This COACH release allows to prototype - and to generate the FPGA-SoC. - The main restrictions are: - 1) Only the neutral architectural template is supported, - 2) HAS is not available (but prototyping with virtual coprocessors is available), - 3) Enhanced communication schemes are not available. - 4) ASIP compilation flow is not available. - \item[Milestone 3 ($T0+18$)] - The second COACH release. At this step most of the COACH features are available. - A preliminary version of the ASIP synthesis flow is supported, for a - simple extensible MIPS model. The main restriction is that COACH can not yet - generate FPGA-SoC for \altera and \xilinx architectural templates. - The others restriction is that the HAS tools are not yet fully operational. -\item[Milestone 4 ($T0+27$)] - The pre-release of the COACH project. The full design flow is supported. - The main restrictions are: - 1) Automatic frequency calibration of coprocessors is not available. - 2) Automatic HPC set up is not yet available. - 3) NIOS processor instruction set extension is supported, but only for user - specified patterns. - 4) GAUT enhancements are not available. -\item[Final Release ($T0+36$)] -\end{description} -This organisation allows the project to globally progress step by step mixing -development and demonstrator deliverables. -Hence, demonstrator feed-back will arrive early and so the risk to point out -incompatibility at the integration phase is significantly reduced. -The risks that have been identified at the beginning of the project are the following: -\begin{description} - \item[\xcoach format ({\NOVERSspecXcoachDoc}, {\NOVERSspecXcoachToCA})] - Partners have to agree on a convenient exchange format for all tools involved. - Because all the HAS tools rely on it, the \xcoach format specification is a - crucial step. - There are no work-around but as mentioned in section~\ref{xcoach-problem} - (page~\pageref{xcoach-problem}) the five academic partners have worked on it - for a full year and a preliminary document already exists. -%\item[\xcoachplus format (\novers{\specXcoachDoc}, -% \novers{\specXcoachToSystemC}, \novers{\specXcoachToVhdl})] -% Its aim is the generation of the coprocessors (hardware \& prototyping model). -% By centralizing the coprocessor generation, it guarantees their functioning -% independently of the used HAS tools. -% Our experience with UGH and GAUT give us confidence in the succes of this -% task. - \item[Virtual prototyping ({\NOVERScsgImplementation})] - In this project, only the virtual prototyping of the neutral architectural - template is supported. - We think that this restriction is not a serious problem. - Indeed the \altera \& \xilinx architectural templates being architecturally close of - the neutral architectural template, an efficient software/hardware partition - on the neutral architectural template is also efficient on the other - architectural templates. - The project will allow an experimental verification of this assumption. -% \item[Virtual prototyping of \altera \& \xilinx architectural templates -% ({\NOVERScsgImplementation})] -% The SoCLib component library contains several SystemC models used for the -% virtual prototyping of the \altera and \xilinx architectural templates -% (NIOS and \xilinxcpu processor cores). -% Nevertheless, at this time we do not know how many IP cores SystemC -% simulation models have to be developped. -% If the workload of this simulation model development is too important, -% virtual prototyping of those architectural templates will not be directly -% supported. -% The three architectural templates being quite similar, the virtual -% prototyping will use the neutral architectural template. - \item[VCI/AVALON \& VCI/\xilinxbus bridges ({\NOVERShpcAvalonBridge}, {\NOVERShpcPlbBridge})] - These bridges may decrease the efficiency of the \altera \& \xilinx - architectural templates. - Developing the communication components (MWMR) for the AVALON and \xilinxbus buses - will correct this problem. -% If one of these tasks is impossible or too important or leads to inefficiency, -% it will be abandoned. -% In this case, the neutral architectural template will not be available for HPC and -% a SystemC VCI model corresponding to the PCI/X IP will be developped to allow -% virtual prototyping. -\end{description} -% -Finally the list of all the deliverables is presented on figure~\ref{all-delivrables}. -\begin{figure}[t]\leavevmode\center -{ -\fontsize{7pt}{9pt}\selectfont -\settowidth\desclen{XILINX RTL optimisation (5)} -\def\Sformat#1{\textsc{#1}} -%\hspace*{-2.5mm} -\begin{minipage}{1.0\linewidth} -\input{table_livrable_01.tex} -\hfill\hspace*{1mm}\hfill -\input{table_livrable_02.tex} -\end{minipage} -} -\caption{\label{all-delivrables}All the deliverables} -\end{figure} Index: r/section-ressources.tex =================================================================== --- /anr/section-ressources.tex (revision 386) +++ (revision ) @@ -1,236 +1,0 @@ -\anrdoc{On présentera ici la justification scientifique et technique des moyens -demandés dans le document de soumission A par chaque partenaire et -synthétisés à l'échelle du projet dans la fiche «Tableaux récapitulatifs» -du document de soumission A.\\ -Chaque partenaire justifiera les moyens qu'il demande en distinguant les -différents postes de dépenses.\\ -Pour chaque partenaire on precisera: -\begin{itemize} -\item Equipment: 1) Préciser la nature des équipements* et justifier le - choix des équipements. 2) Si nécessaire, préciser la part de financement - demandé sur le projet et si les achats envisagés doivent être complétés - par d'autres sources de financement. Si tel est le cas, indiquer le - montant et l'origine de ces financements complémentaires.\\ - * Attention: Un devis sera demandé si le projet est retenu pour - financement. -\item Personnel costs - 1) Le personnel non permanent (thÚses, post- doctorants,CDD...) - financé sur le projet devra être justifié. - 2) Fournir les profils des postes à pourvoir pour les personnels à - recruter (1/2 page maximum par type de poste) - 3) Pour les thÚses, préciser si des demandes de bourse de thÚse sont - prévues ou en cours, en préciser la nature et la part de financement - imputable au projet. -\item Subcontracting. Préciser: 1) la nature des prestations - 2) le type de prestataire. -\item Travel. Préciser: 1) les missions liées aux travaux d'acquisition - sur le terrain (campagnes de mesures), - 2) les missions relevant de colloques, congrÚs. -\item Costs justified by internal procedures of invoicing. Préciser la nature - des prestations. -\item Other expense. Toute dépense significative relevant de ce poste - devra être justifiée. -\end{itemize}} -% -\def\resstablestyletitle#1{\begin{small}{\textit{#1}}\end{small}} -% -\def\ressources#1#2#3#4#5{{% - \def\tmp{} - \begin{description} - \setlength{\itemsep}{1pt} - \setlength{\parskip}{0pt} - \setlength{\parsep}{0pt} - \item[Equipment] - \def\cont{#2} - \ifx\cont\tmp\def\cont{No specific equipment acquisition is required for this project.}\fi - \cont - \item[Personnel costs] - #3\\ - \begin{minipage}{\linewidth}\center\input{table_#1_short.tex}\end{minipage} - \item[Subcontracting] No subcontracting costs. - \item[Travel] - The travel costs are associated to project meeting as well as participation to - conferences. The travel costs are estimated to \textbf{#4\%} of the total requested ANR funding. - \item[Expenses for inward billing] - \def\cont{#5} - \ifx\cont\tmp\def\cont{None.}\else\def\cont{% - The costs justified by internal invoicing procedures are evaluated - to \textbf{#5\%} of the total requested ANR funding.}\fi - \cont - %\item[Other working costs] None - \end{description} -}} - -\newcount\mycnt -\def\AcademicPersonalCost#1#2#3#4#5#6#7{ - \mycnt=#4\multiply\mycnt100\divide\mycnt#3 - The #2 effort is \textbf{#3} \hommemois, the table below details it by tasks and the - table in annexe~\ref{table-livrables-#1} (page \pageref{table-livrables-#1}) - details it by deliverables. - The permanent personnels are #5. - The effort due to the non permanent personnels is \textbf{#4} \hommemois - (\textbf{\the\mycnt\%} of the total effort). - The requested funding for non permanent personnels is \textbf{#6\%} of the total ANR - requested funding. - #7 -} -\def\ressourcesForAcademic#1#2#3#4#5{ - \ressources{#1}{#2}{\AcademicPersonalCost{#1}#3}{#4}{#5} -} -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% - -The global effort is \textbf{355} \hommemois (\hommemoislong), -the part of academic partners is \textbf{245} \hommemois (\textbf{69\%} of the global effort) -and the part of the industrial partners is \textbf{110} \hommemois (\textbf{31\%} of the -global effort). -The tables in annexe~\ref{effort:by:livrable} gives this global effort by deliverables, -those of annexe~\ref{effort:by:partner:livrable} shows this global effort by partner and -deliverables.\\ -\textbf{NOTICE:} 1) In these tables and in the following sections the units is the -\hommemois of a senior researcher (post-doc or research engineers). -2) In order to develop and check the FPGA drivers, the partners will by some FPGA boards but -their costs being less than 4000 \euro, they are not mentionned in the following -sections. - - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 1: \mdslong} -\ressources{mds} - {} - { - \mds employees involved in the project are permanent managers, engineers and PhD graduates. - The manpower detail in \hommemois by deliverables is given in - annexe~\ref{table-livrables-mds} (page \pageref{table-livrables-mds}) - and a summary by tasks in the following table. - } - {3.5} - {} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 2: \upmc} -\ressourcesForAcademic - {upmc} - {} - {{\upmc}{52}{24}{Alain Greiner and Ivan Aug\'e}{88}{ - We are looking for a profile with strong skills in SW development and good - knowledge in SoC design and virtual prototyping. - }} - {8}{3.5} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\def\t{\hspace*{.5cm}} -\subsection{Partner 3: \ubs} -\ressourcesForAcademic - {ubs} - {} - {{\ubs}{48}{24}{Philippe COUSSY, Cyrille CHAVET and Dominique HELLER}{85}{ - We are looking for profiles with strong informatic skills, good knowledge - in computer architecture and advanced digital design. - }} - {12}{4} - - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 4: \liplong} -\ressourcesForAcademic - {inria_compsys}{} - {{\lip}{46}{21}{Christophe Alias and Paul Feautrier}{82}{ - \\We are looking for a candidate with both theoretical and - practical skills, that will be able to get a sufficient - understanding of the polyhedral techniques.}} - {12}{4} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 5: \tima} -\ressourcesForAcademic - {tima}{} - {{\tima}{48}{24}{Fr\'ed\'eric P\'etrot, Olivier Muller and Adrien Prost-Boucle}{86}{ - \\We are looking for profiles with strong informatic skills, good knowledge in - computer architecture, and advanced digital design. - }} - {10}{4} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 6: \inria} -\ressourcesForAcademic - {inria_cairn}{} - {{\inria}{51}{27}{ François Charot and Steven Derrien}{84}{ - We are looking for a profile with strong skills in SW development and good - knowledge in computer architecture. - }} - {10}{4} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 7: \bull} -\ressources - {bull} - {} - { The man power detail in \hommemois by deliverables is given in - annexe~\ref{table-livrables-bull} (page \pageref{table-livrables-bull}) - and a summary by tasks in the following table. - \bull employees involved in the project are a manager for 9 \hommemois - and an engineer for 15 \hommemois.} - {3}{} - -% {The design of FPGA board (s) will represent the main equipment cost for Bull -% in COACH. It is estimated at about 10 k\euro (about 12\% of the total -% requested ANR funding) representing the re-design/adaptation of an -% existing FPGA board (the SAM "Simulation Accelerated Module" board).} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Partner 8: \thales} -\ressources - {thales} - {} - { The man power detail in \hommemois by deliverables is given in - annexe~\ref{table-livrables-thales} (page \pageref{table-livrables-thales}) - and a summary by tasks in the following table. - \thales employees involved in the project are a manager for 7 \hommemois, - an engineer for 8 \hommemois and a PHD candidate for 21 \hommemois} - {8}{} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -% -% \begin{landscape} -% \begin{figure} -% \begin{small} -% \settowidth\desclen{XILINX RTL optimisation (5)} -% \def\resstablestyletitle#1{\parbox{\desclen}{\textit{#1}}} -% \begin{minipage}[b]{.47\linewidth}\center -% \input{table_inria_cairn_full.tex}\vspace{.5ex}\\ \inria \vspace{2.5ex}\\ -% \input{table_mds_full.tex}\vspace{.5ex}\\ \mds \\ -% \end{minipage}\hfill\begin{minipage}[b]{.47\linewidth}\center -% \input{table_tima_full.tex}\vspace{.5ex} \\ \tima -% \end{minipage} -% \end{small} -% \caption{\label{table-livrables-1} Man power in \hommemois for the deliverables (1)} -% \end{figure} -% % -% \begin{figure} -% \begin{small} -% \settowidth\desclen{XILINX RTL optimisation (5)} -% \def\resstablestyletitle#1{\parbox{\desclen}{\textit{#1}}} -% \begin{minipage}[b]{.47\linewidth}\center -% \input{table_ubs_full.tex}\vspace{.5ex}\\ \ubs \vspace{2.5ex}\\ -% %\input{table_thales_full.tex}\vspace{.5ex}\\ \thales \\ -% \end{minipage}\hfill\begin{minipage}[b]{.47\linewidth}\center -% \input{table_upmc_full.tex}\vspace{.5ex} \\ \upmc -% \end{minipage} -% \end{small} -% \caption{\label{table-livrables-2} Man power in \hommemois for the deliverables (2)} -% \end{figure} -% \end{landscape} -% % -% %\begin{landscape} -% %\begin{figure} -% %\begin{small} -% %\settowidth\desclen{XILINX RTL optimisation (5)} -% %\def\resstablestyletitle#1{\parbox{\desclen}{\textit{#1}}} -% %\hfill -% %\begin{minipage}[b]{.47\linewidth}\center -% %\input{table_inria_compsys_full.tex}\vspace{.5ex}\\ \lip \vspace{2.5ex}\\ -% %\end{minipage}\hfill -% %\end{small} -% %\caption{\label{table-livrables-2} Man power in \hommemois for the deliverables (3)} -% %\end{figure} -% %\end{landscape} Index: r/table_lip_full.tex.sav =================================================================== --- /anr/table_lip_full.tex.sav (revision 386) +++ (revision ) @@ -1,11 +1,0 @@ -\begin{tabular}{|c|p{3.5cm}||r|r|r||r|}\hline -number & \multicolumn{1}{c||}{title} & \multicolumn{3}{c||}{years } & total \\\cline{3-5} - & & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{2} & \multicolumn{1}{c||}{3} & \\\hline\hline -D230 & \resstablestyletitle{Specification of {\tt xcoach} format} & 7.0 & 3.0 & 0.0 & 10.0 \\\hline - & total Task-2 & 7.0 & 3.0 & 0.0 & 10.0 \\\hline -\hline D430 & \resstablestyletitle{Process generation method} & 5.0 & 0.0 & 5.0 & 10.0 \\\hline -D431 & \resstablestyletitle{Process and FIFO construction} & 20.0 & 20.0 & 20.0 & 60.0 \\\hline - & total Task-4 & 25.0 & 20.0 & 25.0 & 70.0\\\hline -\hline - & total & 32.0 & 23.0 & 25.0 & 80.0 \\\hline -\end{tabular} Index: r/table_lip_short.tex.sav =================================================================== --- /anr/table_lip_short.tex.sav (revision 386) +++ (revision ) @@ -1,8 +1,0 @@ -\begin{center}\begin{small}\begin{tabular}{|c|l||r|r|r||r|}\hline - & title & \multicolumn{3}{c||}{years } & total \\\cline{3-5} - & & \multicolumn{1}{c|}{1} & \multicolumn{1}{c|}{2} & \multicolumn{1}{c||}{3} & \\\hline\hline -Task-2 & Backbone infrastructure & 7.0 & 3.0 & 0.0 & 10.0 \\\hline -Task-4 & HAS front-end & 25.0 & 20.0 & 25.0 & 70.0 \\\hline -\hline - & total & 32.0 & 23.0 & 25.0 & 80.0 \\\hline -\end{tabular}\end{small}\end{center} Index: r/task-backbone.tex =================================================================== --- /anr/task-backbone.tex (revision 386) +++ (revision ) @@ -1,132 +1,0 @@ -\begin{taskinfo} -\let\UPMC\leader -\let\ALL\enable -\end{taskinfo} -% -\begin{objectif} -The objectives of this task are the specification of the designer input, the -definition of the hardware architectural templates and of all the features -that the HAS tools will share. -An other objective is the specification of the framework used to facilitate the -exploitation and the integration of the core engine into an industrial flow. -\end{objectif} -% -\begin{workpackage} -\subtask{Specification of the COACH environment} - This \ST specifies the global COACH environment for the system designer: - the core engine which is seen as a black box associated - with a configuration framework based on Eclipse. - This framework will be integrated into Magillem tool suite. - The deliverables specify - how to feed COACH (the inputs), - how to use COACH (use model), - what is generated (the outputs) - and how the Magillem framework interacts with the core engine. - \begin{livrable} - \itemV{0}{6}{d}{\Supmc}{Use model specification} - This document describes the use model of COACH. It will be a cooperative work. - Its main parts are: - \begin{description} - \item[General overview] (\Supmc) - \item[CSG specification] (\Stima): - here the COACH System Generator is specified: - how the task graph is described, the communication schemes and - its associated API (Application Programming Interface). - The base is the SRL library and the MWMR communication component defined - by the SocLib ANR project. - Nevertheless, these basic schemes will be enhanced to allow more efficient - synthesis. - \item[HAS specification] (\Subs): - this part focuses on the Hardware Accelerator Synthesis. - It specifies how tasks must be written (C/C++ subset) and how - communication schemes must be described for coprocessor synthesis. - \item[Magillem framework specification] (\Smds): - this part specifies the functionalities enabling the interactions between - Magillem and the core engine. - \end{description} - \itemL{6}{12}{d}{\Supmc}{Use model specification}{2:0:0} - \setMacroInAuxFile{useModelSpecification} - The final version of the Use model specification enhanced - with the feed-backs of the demonstrator \STs. - \OtherPartner{0}{12}{\Slip} {1:0:0} - \OtherPartner{0}{12}{\Sinria} {1:0:0} - \OtherPartner{0}{12}{\Stima} {2:0:0} - \OtherPartner{0}{12}{\Subs} {2:0:0} - \OtherPartner{0}{12}{\Sbull} {1:0:0} - \OtherPartner{0}{12}{\Sthales}{1:0:0} - \OtherPartner{0}{12}{\Smds} {2:0:0} - \end{livrable} -% -\subtask{Internal software structure} - \begin{livrable} - \itemL{0}{6}{d}{\Supmc}{COACH internal \ganttlf software architecture}{1:0:0} - \OtherPartner{0}{6}{\Stima} {.5:0:0} - This document lists all the COACH software components and how they cooperate. - It will refine the software architecture presented in - Figures~\ref{archi-hls} and~\ref{archi-hpc}. - \end{livrable} -% -\subtask{\xcoach format} - This \ST specifies the \xcoach and the \xcoachplus formats. - \begin{livrable} - \itemV{0}{6}{d+x}{\Slip}{\xcoach format specification} - \setMacroInAuxFile{specXcoachDocI} - First release of the XML specification of the \xcoach format (DTD) - and its associated documentation allowing to start HLS tools development. - \itemV{6}{12}{d+x}{\Slip}{\xcoach format specification} - \setMacroInAuxFile{specXcoachDocII} - Second release of XML specification of the \xcoach format - taking into account the corrections and modifications that the - developers of HAS tools suggested. - \itemL{12}{18}{d+x}{\Slip}{\xcoach format specification}{4:2:0} - \OtherPartner{0}{18}{\Supmc} {.5:.5:0} - \OtherPartner{0}{18}{\Stima} {.5:.5:0} - \OtherPartner{0}{18}{\Sinria} {.5:.5:0} - \setMacroInAuxFile{specXcoachDoc} - Last release of XML specification of the \xcoach format enhanced with - the expression of loop potential parallelism. -% - \itemV{6}{12}{x}{\Subs}{C2X tool} - \setMacroInAuxFile{specXcoachToCAI} - This deliverable groups 2 tools. - The first one C2X is a GCC plugin that generates a \xcoach description - (defined in {\specXcoachDocI} deliverable) from a C/C++ task description. - The second one X2C regenerates a C description from a \xcoach description. - \itemL{12}{18}{x}{\Subs}{C2X tool}{4:2:0} - \setMacroInAuxFile{specXcoachToCA} - An updated version of C2X and X2C (\specXcoachToCAI) which supports the - \xcoach format defined in the {\specXcoachDoc} deliverable. -% - \itemV{12}{18}{x}{\Supmc}{First release of X2SC} - \setMacroInAuxFile{specXcoachToSystemCI} - The first release of the software tool X2SC that translates \xcoachplus - description to CABA and TLM-DT SystemC module. - \itemL{18}{27}{x}{\Supmc}{X2SC tool}{0:1:.5} - \setMacroInAuxFile{specXcoachToSystemC} - Final release of the former software (\specXcoachToSystemCI). - \itemV{12}{18}{x}{\Subs}{First release of the X2VHDL} - \setMacroInAuxFile{specXcoachToVhdlI} - The first release of the software tool X2VHDL that translates \xcoachplus - description to synthesizable VHDL description. - \itemL{18}{27}{x}{\Subs}{X2VHDL tool}{0:3:2} - \setMacroInAuxFile{specXcoachToVhdl} - Final release of the former software (\specXcoachToVhdlI). - \end{livrable} -% -\subtask{Tool for cell library creation} - Back-end HLS tools use a characterized macro-cell library to build the - micro-architecture of a coprocessor. The characterization of a cell depends - on the target device. The role of this \ST is to define the macro-cells and - to provide a tool that characterizes them automatically by synthesizing them - and by extracting their delays. This is done by using RTL synthesis. - \begin{livrable} - \itemL{0}{6}{d}{\Subs}{Macro-cell definition}{2:0:0} - \OtherPartner{0}{6}{\Supmc} {.5:0:0} - \OtherPartner{0}{6}{\Stima} {.5:0:0} - \setMacroInAuxFile{specMacroCell} - Definition of the macro cells and the file format describing them. - \itemL{6}{12}{x}{\Subs}{Macro-cell library generator}{2:0:0} - Final release of the software tool that generates automatically the - characterized macro-cell library for a FPGA device. - \end{livrable} -\end{workpackage} Index: r/task-backend.tex =================================================================== --- /anr/task-backend.tex (revision 386) +++ (revision ) @@ -1,90 +1,0 @@ -\begin{taskinfo} -\let\UBS\leader -\let\UPMC\enable -\let\TIMA\enable -\end{taskinfo} -% -\begin{objectif} -The objectives of this task are to provide two HAS back-ends and -a tool that adapt the coprocessor frequency to the FPGA-SoC frequency as required -by the processors and the system bus. -\\ -The HAS back-ends as shown in figure~\ref{archi-hls} reads an \xcoach -description and provides an \xcoachplus description (a \xcoach description -annotated with hardware information such as variables binding to registers, -operations bindings to cells/functional units). -%The \xcoach format being generated by the \novers{\specXcoachToCA} deliverable -%and the \xcoachplus being treated by the \novers{\specXcoachToSystemC} and the -%\novers{\specXcoachToVhdl} deliverables, this task strongly depends on task~1. -\par -For the two HAS front-end, this task is based on the already existing HLS tools GAUT and -UGH. These tools \textbf{are complementary and not in competition} because they -cover respectively data and control dominated designs. -\end{objectif} -% -\begin{workpackage} -\subtask{Integration of UGH \& GAUT HLS tools to COACH} - This adaptation will be done incrementally in three steps: - \begin{enumerate} - \item Make tools to read \xcoach format defined in {\NOVERSspecXcoachDoc} deliverable. - \item Make tools to recognize the API of task communication defined in - {\NOVERSuseModelSpecification} deliverable. - \item Make tools to write \xcoachplus format to let - {\NOVERSspecXcoachToSystemC} deliverable generate the SystemC model and - {\NOVERSspecXcoachToVhdl} deliverable generate the synthesizable VHDL description. - \end{enumerate} - \begin{livrable} - \itemV{6}{12}{x}{\Stima}{UGH integration} - UGH release that reads \xcoach format. - \itemV{12}{18}{x}{\Stima}{UGH integration} - UGH release that interprets the task communication API. - \itemV{18}{27}{x}{\Supmc}{UGH integration} - UGH release that writes \xcoachplus format. - \itemL{27}{36}{x}{\Stima}{UGH integration}{3:3:1} - \OtherPartner{0}{12}{\Supmc}{1:2.5:1} - UGH release taking into account demonstrator's feedback. -% - \itemV{6}{12}{x}{\Subs}{GAUT integration} - GAUT release that reads \xcoach format. - \itemV{12}{18}{x}{\Subs}{GAUT integration} - GAUT release that interprets the task communication API. - \itemV{18}{27}{x}{\Subs}{GAUT integration} - GAUT release that writes \xcoachplus format. - \itemL{27}{36}{x}{\Subs}{GAUT integration}{7:6:3} - \setMacroInAuxFile{gautFinal} - GAUT release taking into account demonstrator's feedback. - \end{livrable} -% -\subtask{Coprocessor frequency adaptation} - In FPGA-SoC, the frequency is given by the processor(s) and the system BUS. The coprocessors - generated by HLS synthesis must respect this frequency. However, the HLS tools can not - guarantee that the micro-architectures they generate accurately respect this - frequency. This is especially the case when the target is a FPGA device, because the - delays are really known only after the RTL synthesis and that estimated delays used - by the HLS are very inaccurate. The goal of this \ST is to provide a tool that adapts - the coprocessors frequency to the FPGA-SoC frequency after the coprocessor RTL - synthesis. - \begin{livrable} - \itemV{0}{12}{d}{\Supmc}{Frequency calibration} - A document describing the set up of the coprocessor frequency calibration. - \itemV{12}{27}{x}{\Supmc}{Frequency calibration} - A VHDL description of hardware added to the coprocessor to enable the calibration. - \itemL{27}{33}{x}{\Supmc}{Frequency calibration}{1:1:4} - \setMacroInAuxFile{freqCalibrationVhdl} - The frequency calibration software consists of a driver in the FPGA-SoC operating - system and of a control software. - \end{livrable} -% -\subtask{GAUT enhancement} - \begin{livrable} - \itemV{18}{27}{d}{\Subs}{GAUT enhancement} - Specification of GAUT enhancements. - The first ones is to support new constraints and objectives. - The second one is a Design Space Exploration framework, GAUT will be - able to use synthesis feed-back informations in order to explore the - design space and to generate optimized architectures. - \itemL{27}{36}{x}{\Subs}{GAUT enhancement}{0:5:4} - Integration of these enhancements into the final GAUT release - ({\gautFinal} deliverable). - \end{livrable} -\end{workpackage} Index: r/task-csg.tex =================================================================== --- /anr/task-csg.tex (revision 386) +++ (revision ) @@ -1,88 +1,0 @@ -\begin{taskinfo} -\let\UPMC\leader -\let\TIMA\enable -\let\MDS\enable -\end{taskinfo} -% -\begin{objectif} -The objectives of this task are to allow the system designer to explore the -design space by quickly prototyping and then to automatically generate the -FPGA-SoC systems. It is described on figure~\ref{archi-csg} and it consists of: -\begin{itemize} - \item The development of the synthesizable models required for the connection - of the coprocessors on the platform bus (2 bridges). - \item The configuration and the development of drivers of the operating - systems (Board Support Package, HAL). - \item The CSG software that generates the SystemC simulators for prototyping - and the FPGA-SoC system including its bitstream and software executable code - (see Figures~\ref{archi-csg} and ~\ref{archi-hls}). -\end{itemize} -A first release will be delivered at $T0+12$ to allow an early start of demonstrator -implementations. -This release will include the standard communication schemes based on SoCLib MWMR component -and support the neutral architectural template for prototyping and hardware generation. -\end{objectif} -% -\begin{workpackage} -\subtask{Bridge implementation} - This \ST deals with the development of the synthesizable models required for - the connection of the coprocessors on the platform bus. - \begin{livrable} - \itemL{18}{30}{h}{\Stima}{HPC hardware \xilinx}{0:3:3} - \setMacroInAuxFile{hpcPlbBridge} - The synthesizable VHDL description of a VCI/\xilinxbus bridge. - \itemL{18}{30}{h}{\Supmc}{HPC hardware \altera}{0:3:3} - \setMacroInAuxFile{hpcAvalonBridge} - The synthesizable VHDL description of an VCI/AVALON bridge. - \end{livrable} -\subtask{OS setup} - This \ST consists of the configuration of the SocLib DNA operating - system and the development of drivers for the hardware architectural templates. - For the \altera and \xilinx architectural templates, the OS must also be ported on - the NIOS2 and \xilinxcpu processors. - \begin{livrable} - \itemV{6}{8}{x}{\Stima}{DNA OS} - Identification and Specification of the drivers required for - the first CSG release using a vendor neutral virtual - prototype. - \itemV{8}{18}{x}{\Stima}{DNA 0S} - Implementation of the identified drivers and integration in - the first CSG release. - \itemL{18}{33}{x}{\Stima}{DNA OS drivers for SoCLib}{4:2:2} - \OtherPartner{6}{33}{\Supmc} {.5:.5:.5} - Final release of the DNA OS drivers for the CSG selected IPs. - \itemL{12}{18}{x}{\Stima}{Driver ports}{0:2:0} - \OtherPartner{6}{33}{\Supmc} {0:2:0} - %\mustbecompleted{TIMA: tima sur \xilinxcpu, UPMC sur Nios} - Final port of the DNA OS on the NIOS2 and \xilinxcpu - processors and CSG platforms, along with the platform - dependant drivers. - \Stima will focus on the platform based on Xilinx IPs, whereas - \Supmc will focus on the Altera related IPs and platform. - \end{livrable} -\subtask{Implementation of CSG} - \begin{livrable} - \itemV{0}{12}{x}{\Supmc}{CSG} - The first software release of the CSG tool that will allow demonstrators to start - working by using the neutral architectural template only for SystemC. - \itemV{12}{18}{x}{\Supmc}{CSG} - The second release of CSG integrates the VHDL driver for the neutral - architectural template, and an integration of an HLS tools - but only for SystemC prototyping. - \itemV{18}{27}{x}{\Supmc}{CSG} - This release extends CSG to FPGA-SoC generation for the \xilinx and - \altera architectural template. - \itemL{27}{36}{x}{\Supmc}{CSG tool}{5:2:3} - \OtherPartner{0}{36}{\Stima}{1:3:2} - \OtherPartner{0}{36}{\Smds}{1:3:3} - \setMacroInAuxFile{csgImplementation} - Final release of CSG enhanced by the demonstrator's feedback. - \\ - The work will be split between the partner as follow: 1) \Supmc will - design the core of CSG, 2) \Stima will design the part concerning the - generation of system software and the configuration of CSG to other OS. - 3) \Smds will focus on interfacing CSG to the IP-XACT format for - generating IP integrable into a IP-XACT flow such as the one defined in the SoCket project and to - configure CSG to new IP or plate-form. - \end{livrable} -\end{workpackage} Index: r/task-demonstrator.tex =================================================================== --- /anr/task-demonstrator.tex (revision 386) +++ (revision ) @@ -1,130 +1,0 @@ -\label{task-demonstrator} -\begin{taskinfo} -\let\MDS\enable -\let\BULL\enable -\let\THALES\leader -\let\LIP\enable -\end{taskinfo} -% -\begin{objectif} -This task groups the demonstrators of the COACH project. -The demonstrators cover various domains and application types to drive -the specification choices and to check most of the COACH features. -\end{objectif} -% -\begin{workpackage} -% -\subtask{\bull HPC demonstrator} - The application that \bull proposes is HPC oriented. - The domain of the application is the treatment of medical images (image noise - reduction and segmentation or registration). - Our expectation from the COACH project is to enhance the \bull HPC solutions that - are currently based on multi-cores and GPUs with fine grain parallelism on FPGA. - \begin{livrable} - \itemV{0}{6}{d}{\Sbull}{\bull demonstrator} - The deliverable is a document that describes the application that will be used as - demonstrator. - \itemV{6}{12}{x}{\Sbull}{\bull demonstrator} - The deliverable is the specification of the demonstrator in COACH input format - defined in the {\NOVERSuseModelSpecification} deliverable. - \itemL{12}{36}{d}{\Sbull}{\bull demonstrator}{2:4:5} - \setMacroInAuxFile{bullAppSpecification} - Validation of the demonstrator, the deliverable is a document - describing the result of the experimentations. - \end{livrable} -% -\subtask{\thales Embedded SoC demonstrator} - The objective of this sub-task is to specify the \thales application and to develop the - high level code. This application is in the domain of surveillance of critical - infrastructures. The objective is to detect and classify the presence of humans in the - restricted area. The algorithm is based on the work of Viola and - Jones~\cite{thales-viola}. It implements in particular a cascade of classifiers - operating on Haar like features, where simple weak classifiers at the beginning of the - cascade reject a majority of void sub-windows, before more complex classifiers - concentrate on potential regions of interest. This application is computation - intensive and also makes an intensive use of binary decision trees to cascade the - filters, which makes it a good candidate to assess the COACH platform. - \\ - Moreover, the higher levels of computing can involve tracking and data fusion between - several camera streams and some other informations. - The targeted system will be composed of one camera connected to a PC. - All the computing part of the application is executed on a FPGA board connected to the - PC. - \begin{livrable} - \itemV{0}{6}{d}{\Sthales}{\thales demonstrator} - \setMacroInAuxFile{trtAppSpecification} - This deliverable is a document that specifies the application. - \itemV{6}{12}{x}{\Sthales}{\thales demonstrator} - The deliverable is the specification of the demonstrator in COACH input format - defined in the {\NOVERSuseModelSpecification} deliverable (milestone M2). - \itemL{12}{27}{x}{\Sthales}{\thales demonstrator}{3:2:2} - Validation of demonstrator for M4 milestone. - The deliverable is the specification of the demonstrator in COACH - milestone M4. - \end{livrable} -% -\subtask{SPEAR-DE adaptation for COACH} - \thales will use its internal software environment tool SPEAR DE to describe the - application. The tool is able to partition and to generate the code for the target. - \\ - In this task, we will adapt SPEAR DE to generate the application description input of - COACH framework. We will also describe the three templates of architecture in order to - be able to partition the application on the architecture. - \begin{livrable} - \itemL{6}{27}{x}{\Sthales}{SPEAR-DE adaptation}{6:7:3} - \setMacroInAuxFile{trtSpearde} - Adaptation of SPEAR-DE for COACH framework. - \OtherPartner{0}{12}{\Slip} {0.5:0.5:0.5} - \end{livrable} -% -\subtask{\mds use case} - The goal of the \mds demonstrator will be to experiment and validate the good integration - of the COACH tools into an industrial SoC design flow for critical systems. This demonstrator will be based on - the standard flow defined in the SoCket project and \mds will use a classical SoC platform - based on the LEON processor and which simulation models are available for free (this will - facilitate the further dissemination of the demonstrators to external prospects). - The required prototypes of IP-XACT generators will be specified and implemented; they will be - generic enough or at least customizable in order to be at the basis of the further deployement into - actual design flows. The objectives of this demonstrator are the following: - \begin{itemize} - \item Validate the IP-XACT packaging of the generated SoC. - \item Experiment the integration of the generated SoC into the top level - (TLM or RTL) of a bigger system. - \item Bring a focus on flow capabilities for requirements traceability - from system properties, down to sub-systems implementation. - \end{itemize} - \begin{livrable} - \itemV{0}{12}{d}{\Smds}{Use case} - \setMacroInAuxFile{mdsAppSpecification} - This deliverable is a document that specifies the demonstrator. - \itemV{12}{27}{x}{\Smds}{\mds demonstrator} - This deliverable is the intermediate demonstrator specified in (\mdsAppSpecification). - \itemL{27}{36}{x}{\Smds}{\mds demonstrator}{6:6:6} - This deliverable is the final demonstrator specified in (\mdsAppSpecification). - \end{livrable} -% -\subtask{Evaluation report} - In this sub-task, \mds, \thales and \bull will evaluate the COACH platform. - The evaluation points are: - 1) the ability to generate a whole VHDL of an embedded system on FPGA for an application - mixing control and data flow aspects; - 2) the performance of the generated system in terms of GOPS; - 3) the design time from a high level description. - \begin{livrable} - \itemV{18}{27}{d+x}{\Smds}{Evaluation} - This deliverable written by \Smds, \Sbull and \Sthales is a document - that synthesizes the results got for the demonstrators - (\NOVERSbullAppSpecification, \NOVERStrtAppSpecification, - \NOVERStrtSpearde, \NOVERSmdsAppSpecification) - using the COACH milestone of T0+18. - \itemL{27}{36}{d+x}{\Smds}{Evaluation}{0:3:3} - \OtherPartner{18}{36}{Sbull}{0:2:3.5} - \OtherPartner{18}{36}{Sthales}{0:4:4.5} - This deliverable is a document that validates and evaluates the COACH final release - for the demonstrators. - %(\NOVERSbullAppSpecification, \NOVERStrtAppSpecification, - %\NOVERStrtSpearde, \NOVERSmdsAppSpecification). - The final code of the application demonstrators (\NOVERSbullAppSpecification, - \NOVERStrtAppSpecification) will be provide. - \end{livrable} -\end{workpackage} Index: r/task-dissemination.tex =================================================================== --- /anr/task-dissemination.tex (revision 386) +++ (revision ) @@ -1,100 +1,0 @@ -\begin{taskinfo} -\let\MDS\leader -\let\ALL\enable -\end{taskinfo} -% -\begin{objectif} -This task relates to the diffusion of the project results. -The classical objective is to ensure the dissemination of the result into the community -by writing papers, -by presenting COACH in trade shows -and by publishing on a public WEB site all the information that a COACH user requires. -The main objective is to prepare the further industrial exploitation of the results. -The deliverables to reach these goals will be: -%\begin{itemize} -% \item The packaging of COACH milestones and final release and their associated -% installation manuals. -% Two versions will be packaged (one open source, one commercial in the -% Magillem environment). -% \item A tutorial. -% \item The user reference manuals. -%\end{itemize} - \textbf{1)} The packaging of COACH milestones and final release and their associated - installation manuals. - Two versions will be packaged (one open source, one commercial in the - Magillem environment). - \textbf{2)} A tutorial. - \textbf{3)} The user reference manuals. -\end{objectif} -% -\begin{workpackage} - \subtask{Packaging of COACH releases} - \begin{livrable} - \itemL{6}{36}{d+x}{\Supmc}{Open source release}{1:.5:.5} - This deliverable deals with the packaging of the open sources milestones and - final releases with their installation manuals and to publish then into the WEB - site. This packaging will be done for standard Unix environments using - the usual open source installation configuration tools (automake, autoconf). - \itemL{6}{36}{d+x}{\Smds}{Commercial release}{1:.5:.5} - This deliverable deals with the elaboration of a release of COACH integrated - into the Magillem environment. - \end{livrable} -% - \subtask{Tutorial} - \label{subtask-tutorial} - The application of this tutorial will be a Motion JPEG application. - \begin{livrable} - \itemV{6}{12}{d+x}{\Supmc}{Tutorial} - It will illustrate the features of T0+12 milestone, especially:\hfill - \begin{description} - \item[HPC] This tutorial section shows how an application can be split into - two communicating parts (PC part and FPGA-SoC part) and how to - measure the partition quality. - \item[SoC] This tutorial section shows how FPGA-SoC part can be described as - communicating task graph and how a promising task graph can be obtained. - \end{description} - \itemL{30}{36}{d}{\Supmc}{Tutorial}{1.5:0.0:1.0} - \OtherPartner{30}{36}{\Smds}{1.5:0:1} - The final release of the tutorial. It will be completed with sections - that illustrate: - \begin{description} - \item[HAS (\Supmc)] This section shows how a task can be migrated to - coprocessor using HAS tools and how FPGA-SoC can be generated and run to - FPGA. - \item[Inegration (\Smds)] This section is dedicated to the integration of - COACH generated IP into an IP-XACT based design flow such as the one define in the SoCket project for critical systems - and which is generic enough to support a wide range of application domains. - \end{description} - \end{livrable} -% - \subtask{Reference user manuals} - \begin{livrable} - \itemL{21}{27}{d}{\Stima}{CSG User manual}{0:.5:1} - This user manual shows how to generate a complete HW/SW system by using the CSG tool. - \itemL{21}{27}{d}{\Slip}{HAS front-end user manual}{0:.5:1} - This user manual shows how to apply loop transformations to a task. - \itemL{21}{27}{d}{\Sinria}{ASIP user manual}{0:1:1} - This user manual shows how to customize a processor to obtain an ASIP. - \itemL{21}{27}{d}{\Subs}{HLS user manual}{0:.5:1.5} - This user manual shows how a task can be synthesized by using UGH and GAUT tools. - \OtherPartner{12}{36}{\Subs}{0:2:2} - \itemL{21}{27}{d}{\Smds}{Magillem framework \ganttlf user manual}{0:1:1} - This user manual describes how to use COACH within the IP-XACT based Magillem tool suite. - \end{livrable} -% - \subtask{Publications and Communications} - \begin{livrable} - \itemL{12}{36}{d}{\Smds}{Publication, communication}{0:2:3} - \OtherPartner{12}{36}{\Sinria} {0:1:1} - \OtherPartner{12}{36}{\Slip} {0:1:1} - \OtherPartner{12}{36}{\Stima} {0:1:1} - \OtherPartner{12}{36}{\Subs} {0:1:1.5} - \OtherPartner{12}{36}{\Supmc} {0:1:1} - \OtherPartner{12}{36}{\Sbull} {0:.5:.5} - \OtherPartner{12}{36}{\Sthales}{0:1:1} - This deliverable groups the effort to make COACH better known. It consists - mainly in writing/submitting papers and in presenting COACH in to trade - show and workshop and organizing a final white paper. - This white paper will facilitates the dissemination towards industrial prospects. - \end{livrable} -\end{workpackage} Index: r/task-frontend.tex =================================================================== --- /anr/task-frontend.tex (revision 386) +++ (revision ) @@ -1,100 +1,0 @@ -\begin{taskinfo} -\let\LIP\leader -\let\INRIA\enable -\end{taskinfo} -% -\begin{objectif} -The objective of this task is to convert the input specification of -an hardware accelerator, which must be written in a familiar language -(C/C++) with as few constraints as possible, into a form suitable for -the HLS tools (i.e. HAS back-end tools of the COACH project). If the -target is an ASIP, the front-end has to extract -patterns from the source code and convert them into the definition -of an extensible processor. If the target is a process network, the -front end has to distribute the workload and the data sets as fairly -as possible, identify communication channels, and output an \xcoach -description. -\end{objectif} -% -\begin{workpackage} - \subtask{ASIP compiler} - This sub-task aims at providing compiler support for custom instructions - within the HAS front-end. It will take as input the COACH intermediate - representation, and will output an annotated COACH IR containing the custom - instructions definitions along with their occurrence in the application. - \begin{livrable} - \itemV{0}{12}{x}{\Sinria}{ASIP compilation flow} - In this first version of the software, the computations patterns corresponding to - custom instructions are specified by the user, and then automatically extracted (when - beneficial) from the application intermediate representation. - \itemL{12}{27}{x}{\Sinria}{ASIP compilation flow}{6:6:3} - In this second version, the software will also be able to automatically identify - interesting pattern candidates in the application code, and use them as custom - instructions. - \end{livrable} -% - \subtask{Micro-architectural template models for ASIP} - In this sub-task, we provide micro-architectural template models for the two target - processor architectures (NIOS-II and MIPS) supported within the COACH-ASIP design flow. - For each processor, we provide a simulation model (System-C) and a synthesizable model (VHDL) - of the architecture, along with its architectural extensions - \begin{livrable} - \itemV{0}{12}{x}{\Sinria}{SystemC for extensible MIPS } - { A SystemC simulation model for a simple extensible MIPS architectural template } - \itemL{12}{27}{x}{\Sinria}{SystemC for extensible MIPS}{3:2:1} - {A SystemC simulation model for an extensible MIPS with a tight architectural integration of - its instruction set extensions} - \itemV{3}{18}{h}{\Sinria}{VHDL for an extensible MIPS} - {A synthesizable VHDL model for a simple extensible MIPS architectural template} - \itemL{18}{27}{h}{\Sinria}{VHDL for extensible MIPS}{8:8.5:3} - {A synthesizable VHDL model for an extensible MIPS with a tight architectural integration of - its instruction set extensions} - \itemL{27}{36}{d}{\Sinria}{Evaluation report }{0:0:3} - {An evaluation report with quantitative analysis of the performance/area trade-off induced by - the different approaches} - \end{livrable} -% - \subtask{Automatic parallelization and memory optimization} - This sub-task aims at providing a source-level optimizer in front the - HLS back-end tools. The optimizations are threefold: - \begin{itemize} - \item Extraction of parallelism in polyhedral loops and conversion - into a process network. - \item Minimization of intra-process local memory - \item Construction of inter-process FIFOs - \end{itemize} - We will design these methods by using polyhedral techniques, as we did - in the past for pure HPC optimizations. The program model is typically - regular programs where loop bounds, conditions and array indices are - affine functions. In a second part, we will extend the program model - by using conservative approximations. - \begin{livrable} - \itemV{0}{6}{d}{\Slip}{Method, Preliminary Definition} - Description and specification of a process construction method for programs with - polyhedral loops. - \itemV{6}{12}{x}{\Slip}{Process construction} - Preliminary implementation in the Syntol framework. - At this step the software will just implement a single constructor. - \itemL{30}{36}{d+x}{\Slip}{Process generation method}{3:0:3} - Final assessment of the method and improved version of the specification. -% - \itemV{6}{12}{d}{\Slip} {Arrays and FIFO} - Description and specification of the FIFO construction method - and the local memory optimization method. - \itemV{12}{18}{d+x}{\Slip} {Arrays and FIFO} - Preliminary implementation in the Bee framework. - Conversion of the input and output of Bee to the \xcoach format. - At this step, only local memory optimization will be available. - \itemL{18}{30}{d+x}{\Slip}{Arrays and FIFO}{1.5:2.0:1} - Final assessment of the method and improved version of the specification. -% - \itemV{18}{30}{d+x}{\Slip}{Non-polyhedral extension} - Extension of automatic parallelization and memory optimization - to non-polyhedral loops. Implementation in the Bee framework. - \itemL{30}{36}{d+x}{\Slip} {Non-polyhedral extension}{0.0:9.0:13.0} - Final release taking into account the feedbacks from the - demonstrator \STs. - \end{livrable} -% -\end{workpackage} - Index: r/task-hpc.tex =================================================================== --- /anr/task-hpc.tex (revision 386) +++ (revision ) @@ -1,73 +1,0 @@ -% vim:set spell: -% vim:spell spelllang=en: - -\begin{taskinfo} -\let\BULL\leader -\let\UPMC\enable -\let\TIMA\enable -\let\XILINX\enable -\end{taskinfo} -% -\begin{objectif} -This task deals with the COACH HPC feature that consists in accelerating an existing -application running on a PC by migrating critical parts into a SoC implemented on an -FPGA plugged to the PC PCI/X bus (figures~\ref{coach-flow} and \ref{archi-hpc}). -It consists in: -\begin{itemize} -\item Specifying and implementing the communication schemes between the software - part running on the PC and the FPGA-SoC. -\item Providing a performance analysis tool helping user in the HPC partitioning - (figure~\ref{archi-hpc}). -\item Providing support for configuration of the FPGA in order to set up the HPC environment. -\end{itemize} -The low level hardware transmission support will be the PCI/X bus which allows high bit-rate -transfers. The reasons of this choice are that both \altera and \xilinx provide PCI/X IP for -their FPGA and that GPU HPC softwares use also it. -%This will allow us at least to be inspired by GPU communication schemes and may be to reuse -%parts of the GPU softwares. -\end{objectif} -% -\begin{workpackage} - \subtask{Implementation of API between PC and FPGA-SoC} - \begin{livrable} - \itemL{0}{6}{d}{\Sbull}{HPC communication API}{3:0:0} - \OtherPartner{0}{6}{\Supmc}{.5:0:0} - \OtherPartner{0}{6}{\Stima}{.5:0:0} - \setMacroInAuxFile{hpcCommApi} - Specification of the API. - \itemL{6}{12}{x}{\Supmc}{HPC partitioning helper}{1:0:0} - \setMacroInAuxFile{hpcCommHelper} - A library implementing the communication API defined in the {\hpcCommApi} deliverable. - This library is dedicated to help the end-user to partition an application for HPC. - \itemL{21}{27}{x}{\Stima}{HPC API for Linux}{0:2:1.5} - \OtherPartner{21}{27}{\Supmc}{0:1.5:1.0} - \OtherPartner{21}{27}{\Sbull}{0:0.5:0.5} - \setMacroInAuxFile{hpcForLinux} - This deliverable groups all the software components to implement the - HPC communication API (\NOVERShpcCommApi). - \Supmc will develop the Linux part (a C library and a LINUX module), - \Stima will develop the FPGA-SoC part (a DNA driver), - \Sbull will check this implementation on its demonstrator (\NOVERSbullAppSpecification). - \end{livrable} -% -\subtask{SystemC model of the PCI/X} - This \ST deals with the implementation of SystemC modules - required by the neutral architectural template for using the PCI/X IP of \altera and \xilinx. - \begin{livrable} - \itemL{21}{27}{h}{\Supmc}{PCI/X traffic generator}{0:1:1} - The SystemC description of a component that generates PCI/X traffic. It is - required to prototype FPGA-SoC dedicated to HPC. - \end{livrable} -% -\subtask{HPC environment set up} -% It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library. - \begin{livrable} - \itemL{18}{36}{x}{\Stima}{Support for HPC \ganttlf environment set up}{0:3:3} - Modification of the CSG software to set-up the HPC environment. - The objective is to run easily HPC application and the main features are: - automatic calibration of coprocessors (\freqCalibrationVhdl), automatic download of - SoC on FPGA (bitstream and application loader), starting the PC and FPGA - part of the HPC application. - \end{livrable} -% -\end{workpackage} Index: r/task-management.tex =================================================================== --- /anr/task-management.tex (revision 386) +++ (revision ) @@ -1,55 +1,0 @@ -\begin{taskinfo} -\let\MDS\leader -\let\ALL\enable -\end{taskinfo} -% -\begin{objectif} -This task relates to the monitoring of the COACH project. Its main objectives are: -\begin{itemize} -%\setlength{\itemsep}{1pt}\setlength{\parskip}{0pt}\setlength{\parsep}{0pt} -\item To ensure the appropriate progress of the project, -\item To coordinate the scientific and technical cooperation between the partners, -\item To manage and monitor the scientific and technical work and progress in the tasks, -\item To verify the conformance to agreed budget and time scales, -\item To prepare periodic progress reports in order to control the overall progress of the - project, -\item To organize the project meetings, -\item To set up a shared development infrastructure as a version control system and - development WEB site. -\end{itemize} -\end{objectif} -% -\begin{workpackage} - \subtask{Project management} - \begin{livrable} - \itemL{0}{6}{d}{\Smds}{Consortium agreement}{1:0:0} - A document describing the consortium agreement, signed by all the partners. - \itemL{0}{36}{d}{\Smds}{Global project management}{1:1:1} - Global management of the project at all the - levels: progress monitoring, record keeping, meeting organization, review - organization, the writing of the review reports. - \itemL{0}{36}{}{\Smds}{Local project management}{.5:.5:.5}% - \OtherPartner{0}{36}{\Supmc} {.5:.5:.5}% - \OtherPartner{0}{36}{\Subs} {.5:.5:.5}% - \OtherPartner{0}{36}{\Stima} {.5:.5:.5}% - \OtherPartner{0}{36}{\Slip} {.5:.5:.5}% - \OtherPartner{0}{36}{\Sinria} {.5:.5:.5}% - \OtherPartner{0}{36}{\Sthales}{.5:.5:.5}% - \OtherPartner{0}{36}{\Sbull} {.5:.5:.5}% - Project management at the partner level. It includes mainly the progress - monitoring, the record keeping, the participation to the project meetings - and the communication with the project leader and the other partners. - \end{livrable} - \subtask{Management of the development infrastructure} - \begin{livrable} - \itemV{0}{6}{x}{\Supmc}{Development \& dissemination infrastructure (setup)} - Setup of the development infrastructure. It consists mainly of - a version control system, a web site and a wiki. - \itemL{6}{36}{x}{\Supmc}{Development \& dissemination \ganttlf infrastructure}{1:.5:.5} - The management of the development infrastructure consists mainly of - adding and suppressing accounts, retrieving forgotten passwords, adding - conference publications to the project web site, creation and closing development - branches, backup, restoration, .... - \end{livrable} -\end{workpackage} -% Index: r/wp.txt =================================================================== --- /anr/wp.txt (revision 386) +++ (revision ) @@ -1,252 +1,0 @@ - -************************************************************************************************************** -Work package 1 : Specification de l'architecture logicielle de COACH et outils communs: - -TASK-1 LIP6+ALL Specification de COACH au niveau du concepteur de systeme: - COACH est une boite noire, les entrées, les sorties, le flot - de conception préconisé, Définition de l'architecture du MP-SoC et ses 3 mappings - 0+6 LIP6 Livrable-1: un document - -TASK-2 LIP6+ALL Structure interne de COACH. - 0+6 LIP6 Livrable: un document - -TASK-3 LAB-STIC+ALL Définition du language commun annoté (xfg: xlm flow graph) - 0+6 LIP Livrable 1: V0 un document, une dtd - 0+12 LIP Livrable 1: V1 un document, une dtd - 0+18 Livrable 1: V2 expression du potentiel des boucles - - 0+12 LAB-STIC Livrable 2: VO gcc2coach, coach2c - 0+18 LAB-STIC FI gcc2coach, coach2c - 0+18 LIP6 Livrable 3: VO coach2systemc - 0+24 LIP6 FI coach2systemc - LAB-STIC : Livrable 4: V0 0+18 coach2vhdl - V1 : 0+24 - FI : 0+32 - -TASK-4 LAB-STIC+ALL Définition et description des cellules de base et de leur caractéristques. - 0+6 LAB-STIC Livrable 1: un document - 0+12 LAB-STIC Livrable 2: outil de caractéristion automatique - -************************************************************************************************************** -Work package 2 : Outils de conception systemes: - -TASK-1 LIP6 Mutek Operating sytem - 0+12 LIP6 Livrable 1: OS pour Embedded System - 0+30 LIP6 Livrable 2: OS pour HPC (driver PCI/X) et reconfiguration dynamique - -TASK-2 TIMA DNA Operating sytem - 0+12 TIMA Livrable 1: OS pour Embedded System - 0+30 TIMA Livrable 2: OS pour HPC (driver PCI/X) et reconfiguration dynamique - -TASK-3 LIP6+ALL Definition de l'entrée de CSG (Coach System Generator): - la syntaxe d'entrée TCG, architecture, - les primitives de communication entre taches - (variable globale, canaux, tampon ping-pong). - 0+6 LIP6 Livrable 1: document - 0+12 LIP6 Livrable 2: Executable sans reconfiguration: gestion des 3 architectures. - 0+30 TIMA+LIP6 Livrable 3: CSG avec reconfiguration +++++ Ajouter CDP-2-3 - -TASK-4 LIP6 Composants matériels de l'architecture SOCLIB + composants génériques - 0+18 LIP6 Livrable 1: VHDL synthetisable des composants VCI : MWMR, IRQ. -wrapper - 0+18 IRISA? Livrable 2: wrapper SystemC VCI/AVALON - 0+18 IRISA? Livrable 3: wrapper VHDL synthé VCI/AVALON - 0+18 TIMA? Livrable 4: wrapper SystemC VCI/PLB - 0+18 TIMA? Livrable 5: wrapper VHDL synthé VCI/PLB - - 0+18 CITI Livrable 6: VHDL synthetisable d'un composant VCI MWMR++ (DMA intelligent) - 0+18 CITI Livrable 7: modèle SystemC d'un composant MWMR++ VCI(DMA intelligent) - 0+18 LAB-STICC Livrable 8: VHDL synthetisable d'un composant spatio-temporel - - -sans wrapper - 0+18 TIMA Livrable 2: VHDL synthetisable des composants PLB :MWMR, IRQ. - 0+18 TIMA Livrable 3: modèle SystemC des composants PLB :MWMR, IRQ. - 0+18 IRISA? Livrable 4: VHDL synthetisable des composants AVALON : MWMR, IRQ. - 0+18 IRISA? Livrable 5: modèle SystemC des composants AVALON :MWMR, IRQ. - - 0+18 CITI Livrable 6: VHDL synthetisable d'un composant VCI MWMR++ (DMA intelligent) - 0+18 CITI Livrable 6: VHDL synthetisable d'un composant PLB MWMR++ (DMA intelligent) - 0+18 CITI Livrable 6: VHDL synthetisable d'un composant AVALON MWMR++ (DMA intelligent) - 0+18 CITI Livrable 6: modèle SystemC d'un composant MWMR++ VCI(DMA intelligent) - 0+18 CITI Livrable 6: modèle SystemC d'un composant MWMR++ PLB (DMA intelligent) - 0+18 CITI Livrable 6: modèle SystemC d'un composant MWMR++ AVALON(DMA intelligent) - - 0+18 LAB-STICC Livrable 7: VHDL synthetisable d'un composant spatio-temporel - -TASK-5 TIMA Composants matériels de l'architecture Xilinx - 0+18 TIMA Livrable 1: modele systemC des composants MWMR, IRQ. - 0+20 TIMA Livrable 2: VHDL synthetisable des composants MWMR, IRQ. - -TASK-6 IRISA Composants matériels de l'architecture Altera - 0+18 IRISA Livrable 1: modele systemC des composants MWMR, IRQ. - 0+20 IRISA Livrable 2: VHDL synthetisable des composants MWMR, IRQ. - -************************************************************************************************************** -Work package 3 : Outils de synthese front-end (polyedrique et ASIP) - -TASK-1 IRISA Extraction de motifs et regénération au format COACH annoté - 0+18 Livrable 1: V0 Intégration manuelle des motifs - 0+24 FI Intégration automatique des motifs (architecture-dépendant) - -TASK-2 IRISA Définition d'un modele simplifie de micro-architecture capable d'éxecuter des motifs issues de la tâche 1 - 0+12 Livrable 1: Modèle SystemC du MIPS extensible - 0+18 Livrable 1: Modèle VHDL du MIPS extensible - - 0+12 Livrable 2: Modèle SystemC du NIOS extensible - 0+18 Livrable 2: Modèle VHDL NIOS extensible - - 0+12 Livrable 3: Modèle SystemC du µblaze extensible ?? - 0+18 Livrable 3: Modèle µBlaze extensible ??? - - -TASK-3 IRISA Définition d'un modele complexe de micro-architecture - 0+24 Livrable 1: Modèle SystemC du MIPS extensible - 0+24 Livrable 1: Modèle VHDL du MIPS extensible - 0+36 Livrable 2: Rapport d'evaluation - - -TASK-4 LIP-ALL Exploitation des boucles Polyedriques - 0+12 Outil d'ordonnancement - 0+18 Outil d'exploration des transformations - 0+24 generation du code xfg etendu V1 - 0+30 gestion de la memoire et contraction des tableaux - 0+34 generation du code xfg etendu V2 - -************************************************************************************************************** -Work package 4 : Outils de synthese back-end (UGH, GAUT) - -TASK-1 LIP6/TIMA Adaptation de UGH a COACH - 0+18 TIMA Livrable 1: executable(lire du xcoach) - 0+18 TIMA Livrable 2: executable(ecrire du xcoach annote) - -TASK-2 LIP6/TIMA évolution de UGH. - 0+18 LIP6 Livrable 1: executable UGH qui tient compte des primitives d'IO definies - dans le WP2-T3 - 0+?? TIMA Livrable 2: executable UGH qui peut generer une architecture sans que les assignations - des variables sur les registres soient explicites. - -TASK-3 LAB-STICC Adaptation de GAUT a COACH - 0+18 Livrable 1: executable(lire du xcoach) - 0+18 Livrable 2: executable(ecrire du xcoach annote) - -TASK-4 LAB-STICC évolution de GAUT - 0+18 Livrable 1: prise en compte du modèle CDFG - 0+?? Livrable 2: génération d'architecture multi-clock. - 0+?? Livrable 3: synthése hierachique - -TTASK-5 LIP6 Calibrage de la fréquence des coprocesseurs - 0+6 LIP6 Livrable 1: document - 0+12 LIP6 Livrable 2: VHDL synthetisable de la FSM calibrable dynamiquement - 0+20 LIP6 Livrable 3: logiciel de calibrage (cote OS et cote PC). - - -************************************************************************************************************** -Work package 5 : Interlogiciel de communication PC/Accélérateur: - -TASK-1 LIP6+ALL Définition des protocoles de communication entre l'application qui - tourne sur le PC et le TCG qui tourne sur l'accélérateur. - 0+6 LIP6 Livrable 1: Document. - -TASK-2 LIP6 Outils d'aide au bi-partitionnement (mesure de l'efficacité) - 0+12 LIP6 Livrable 1: Librairie C de communication contenant du code permettant - d'estimer l'efficacite. - -(TASK inutile si bridge) -TASK-3 ???? HW pour l'architecture SOCLIB - 0+?? ???? Livrable: VHDL synthetisable d'un pont VCI/Avalon - 0+?? TIMA Livrable: VHDL synthetisable d'un pont VCI/Bus-xilinx - -TASK-4 ???? Sofware pour HPC - 0+?? ???? Livrable 1: driver PCI/X de IP Altera - 0+?? TIMA Livrable 2: driver PCI/X de IP Xilinx - 0+20 LIP6 Livrable 3: Implantation du protocole deifini en TASK-1 du cote PC/Linux - et SOC. - - -************************************************************************************************************** - ---------------------------------------------------------------------------------- -Annexe 1 -Actions de base determinees lors d'une reunion LIP6/TIMA ---------------------------------------------------------------------------------- - - HLS : -UBS+TOUS *1) Définition des cellules et calibrage en fonction des cibles (WP1-T4) -LIP6 *2) Calibrage de la fréquence des coprocesseurs -TOUS *3) Définition de la représentation intermédiaire commune (WP1-T3) -TOUS *4) Définition de la représentation intermédiaire annotée, en vue (WP1-T3) - de génération de SystemC et VHDL -UBS *5) gcc2xml-coach, xml-coach2c (WP1-3) - - pilotage du front-end gcc -LIP6 *6) xml-coach2SystemC (WP1-3) -TIMA *7) xml-coach2VHDL (WP1-3) - - UGH: -LIP6+TIMA *1) Extension des primitives de communication (WP2-T3) - - variables globales, scalaires et tableaux - - pipeline lecture/calcul/écriture en utilisant des - primitives genre aio_read/aio_write/aio_return - -TIMA *2) génération automatique du DDP en fonction du comportement - relacher un peu les contraintes syntaxiques (WP4-T2) - - 3) n'apparait pas dans les WP inclus implicite dans (WP4-T2 ou T1). -TIMA+LIP6 *3) alléger la dépendance syntaxique entre le C et le DDP - - associer un ensemble de variables à un RGF - - ajout automatique des registres -TIMA *4) Utilisation du xml à la place du front-end gcc actuel (WP4-T1) - donc en pratique du xml-coach2vpn -LIP6 *5) Génération du xml-coach annoté (WP4-T1) - - RECONFIGURATION DYNAMIQUE PARTIELLE: -LIP6+TIMA *1) Introduction de la notion de conteneur : définition, (WP2-T3) - structuration, fusion, ... - Bitstream correspondants -TIMA *2) Gestion de la reconfiguration dynamique partielle pour - optimiser l'utilisation des ressources FPGA -TIMA *3) Définition de la gestion des bitstreams avec des copies - locales et stockage dans les hiérarchies mémoires -LIP6+TIMA *4) Implantation sur DSX : connaissance de la notion de conteneur (WP2-T3-L3) -TIMA+LIP6 *5) Impact sur l'OS (chargement dynamique d'applications ou de - tâches) (WP2-T1/T2-L2) - - TOOLING FOR EMBEDDED - CSG (Coach System Generator) : -TOUS *1) Définition d'un gabarit architectural (WP1-T1) -TOUS *2) Définition de 3 mappings possibles : (WP1-T1) - soclib vhdl, xilinx et altera (en DSX) -LIP6 *3) Introduire la notion de variables partagées dans DSX (WP2-T3) - - qui a le droit d'écrire une variable partagée ? -LIP6+TIMA *4) Choix et fourniture des OS (WP2-T1/2-L1) et HW (WP2-T4/5/5) qui va avec -+TOUS - Etude des RAMLOCKS vs LL/SC - - Controleur d'interruption - - ... - - TOOLING FOR HPC -LIP6 *1) Définition des protocoles entre l'OS du PC et l'OS du SoC (W5-T1) -LIP6 *2) Outil de mesure de l'efficacité d'un bi-partitionnement de (W5-T2) - l'application -LIP6+TIMA+ *3) Connexion hw entre PC et SoC : pci-express (WP5-T3) -IRISA bridge os/pci-express/avalon-plb/vci - (nécessite différentes implantations pour les - différentes cartes + drivers correspondant) -LIP6 *4) Implantation du protocole et du loader : (WP2-T1/2-L2), WP5-T4-L3 - lib unix, driver linux, driver os-soc - - ---------------------------------------------------------------------------------- -Annexe 2 ---------------------------------------------------------------------------------- -____________________________________________________________________________________________________ - |ICU Avalon |ICU Xilinx |MWMR Avalon |MWMR Xilinx |NIOS |MICROBLAZE | -________|_______________|_______________|_______________|_______________|_______________|___________| -SystemC |IRISA |TIMA |IRISA |TIMA |? |? | -________|_______________|_______________|_______________|_______________|_______________|___________| -VHDL |IRISA |TIMA |IRISA |TIMA |Altera |Xilinx | -________|_______________|_______________|_______________|_______________|_______________|___________| - - -François charot (IRISA) : développeur des composants soclib compatibles Avalon - ----------------------------------------------------------------------------------