Index: /anr/section-2.2.tex
===================================================================
--- /anr/section-2.2.tex	(revision 203)
+++ /anr/section-2.2.tex	(revision 204)
@@ -25,7 +25,11 @@
 COACH outcome will contribute to strengthen Europe's competitive position by developing
 technologies and methodologies for product development, focusing (in compliance with the
-scope of the above program) on technologies, engineering methodologies, novel tools,
-methods which facilitate resource use efficiency. The approaches and tools to be developed 
-in COACH will enable new and emerging information technologies for the development,
+%scope of the above program) on technologies, engineering methodologies, novel tools,
+%methods which facilitate resource use efficiency. The approaches and tools to be developed 
+%in COACH will enable new and emerging information technologies for the development,
+%methods which facilitate resource use efficiency. The COACH approaches and tools
+scope of the above program) on technologies, engineering methodologies, novel tools
+which facilitate resource use efficiency. The COACH approaches and tools
+will enable new and emerging information technologies for the development,
 manufacturing and integration of devices and related software into end-products.
 %%%
@@ -34,20 +38,26 @@
 \begin{description}
   \item[SOCLIB]
-    The SoCLib ANR platform (2007-2009) is an open infrastructure developped by
-    10 academic laboratories and and 6 industrial companies.
+    The SoCLib ANR platform (2007-2009) is an open infrastructure
+    for system level virtual prototyping of shared memory, multi-processors
+    architectures. It provides tools to map multi-tasks software application on these
+%    The SoCLib ANR platform (2007-2009) is an open infrastructure developped by
+%    10 academic laboratories and and 6 industrial companies.
     (TIMA, LIP6, Lab-STICC, IRISA, ENST, CEA-LIST, CEA-LETI, CITI, INRIA-Futurs, LIS) and 6 
     industrial companies (Thales Communications, Thomson R\&D, STMicroelectronics, Silicomp, MDS, TurboConcept). 
-    It supports system level virtual prototyping of shared memory, multi-processors
-    architectures, and provides tools to map multi-tasks software application on these
-    architectures, for reliable performance evaluation.
+%    It supports system level virtual prototyping of shared memory, multi-processors
+%    architectures, and provides tools to map multi-tasks software application on these
+%    architectures, for reliable performance evaluation.
     The core of this platform is a library of SystemC simulation models for 
     general purpose IP cores such as processors, buses, networks, memories, IO controller.
     The platform provides also embedded operating systems and software/hardware
     communication middleware.
+%    The synthesisable VHDL models of IPs are not part of the SoCLib platform, and
+%    this project enhances SoCLib by providing the synthesisable VHDL models required
+%    for FPGA synthesis.
     The synthesisable VHDL models of IPs are not part of the SoCLib platform, and
-    this project enhances SoCLib by providing the synthesisable VHDL models required
-    for FPGA synthesis.
-  \item[ROMA] The ROMA ANR project (2007-2010)
-    involving IRISA (CAIRN team), LIRMM, CEA List THOMSON France R\&D,
+    this project enhances SoCLib by providing them.
+%  \item[ROMA] The ROMA ANR project (http://roma.irisa.fr, 2007-2010)
+%    involving IRISA (CAIRN team), LIRMM, CEA List THOMSON France R\&D,
+  \item[ROMA] The ROMA ANR project~\cite{roma}
     proposes to develop a reconfigurable processor, exhibiting high
     silicon density and power efficiency, able to adapt its computing
@@ -59,8 +69,10 @@
     ANR project and the ongoing joint INRIA-STMicro
     Nano2012 project to adapt existing pattern extraction algorithms
-    and datapath merging techniques to the synthesis of customized
-    ASIP processors.
+    and datapath merging techniques to ASIP synthesis.
+%    and datapath merging techniques to the synthesis of customized
+%    ASIP processors.
   \item[TSAR]
-    The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and the \upmc targets the design of a 
+%    The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and the \upmc targets the design of a 
+    The TSAR MEDEA+ project (2008-2010) targets the design of a 
     scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib
     plaform for virtual prototyping. The COACH project will benefit from the synthesizable VHDL 
@@ -75,5 +87,6 @@
 \parlf\noindent
 The laboratories involved in the COACH project have a well estabished expertise
-in the following domains:
+%in the following domains:
+in the domains:
 \begin{itemize}
   \item 
@@ -130,5 +143,10 @@
 % IA2PC: comme ce sont des axes tertiaire, il faut faire + court que primaire et
 % IA2PC: secondaire.
-\item[Axis 3 \& 5] \textit{Robotique et contr\^{o}le/commande} and \textit{S\'{e}curit\'{e} et suret\'{e}} \\
+%VERS 3
+\item[Axis 3] \textit{Robotique et contr\^{o}le/commande} \\
+Manufacturing technology employs more and more SoC.
+COACH will permit to design such complex digital systems.
+\textbf{Thereby COACH indirectly answers to axis 3 too}.
+%\item[Axis 3 \& 5] \textit{Robotique et contr\^{o}le/commande} and \textit{S\'{e}curit\'{e} et suret\'{e}} \\
 %VERS 1
 %Future control applications employ more and more SoC.
@@ -140,7 +158,7 @@
 %computation power. 
 %VERS 2 pour gagner de la place
-Manufacturing, controling, security and safety technologies employ more and more SoC.
-COACH will permit to design such complex digital systems.
-\textbf{Thereby COACH indirectly answers to axis 3 and 5 too}.
+%Manufacturing, controling, security and safety technologies employ more and more SoC.
+%COACH will permit to design such complex digital systems.
+%\textbf{Thereby COACH indirectly answers to axis 3 and 5 too}.
 \end{description}
 %Axis 3 "Robotique et contr\^{o}le/commande}"
@@ -185,5 +203,5 @@
 % efficiency, improved business processes and models. The net results: lower costs, faster response times,
 % better service, and higher revenue.
-\parlf
+%\parlf
 Finally, it is worth to note that this project covers priorities defined by the commission 
 experts in the field of Information Technolgies Society (IST) for Embedded