Index: /anr/Makefile =================================================================== --- /anr/Makefile (revision 20) +++ /anr/Makefile (revision 21) @@ -6,5 +6,5 @@ section-4.1.tex \ architecture-csg.pdf architecture-hls.pdf architecture-hpc.pdf \ - dependence-dev.pdf dependence-test.pdf \ + dependence-task-h.pdf \ section-4.2.tex Index: /anr/anr.sty =================================================================== --- /anr/anr.sty (revision 21) +++ /anr/anr.sty (revision 21) @@ -0,0 +1,87 @@ +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\catcode`\@=11 +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\def\enable{enable} +\def\disable{disable} +\def\leader{leader} +\newenvironment{taskinfo}% +{% +\let\ALL\disable% +\let\IRISA\disable% +\let\CITI\disable% +\let\LIP\disable% +\let\TIMA\disable% +\let\UBS\disable% +\let\UPMC\disable% +\let\BULL\disable% +\let\THALES\disable% +\let\ZIED\disable% +}{% +\ifx\ALL\enable% + \ifx\IRISA\disable\let\IRISA\enable\fi% + \ifx\CITI\disable\let\CITI\enable\fi% + \ifx\LIP\disable\let\LIP\enable\fi% + \ifx\UPMC\disable\let\UPMC\enable\fi% + \ifx\TIMA\disable\let\TIMA\enable\fi% + \ifx\UBS\disable\let\UBS\enable\fi% + \ifx\BULL\disable\let\BULL\enable\fi% + \ifx\THALES\disable\let\THALES\enable\fi% + \ifx\ZIED\disable\let\ZIED\enable\fi% +\fi% +\def\@IRISA{\ifx\IRISA\disable{}\else\ifx\IRISA\enable{*}\else{l}\fi\fi}% +\def\@CITI{\ifx\CITI\disable{}\else\ifx\CITI\enable{*}\else{l}\fi\fi}% +\def\@LIP{\ifx\LIP\disable{}\else\ifx\LIP\enable{*}\else{l}\fi\fi}% +\def\@UPMC{\ifx\UPMC\disable{}\else\ifx\UPMC\enable{*}\else{l}\fi\fi}% +\def\@TIMA{\ifx\TIMA\disable{}\else\ifx\TIMA\enable{*}\else{l}\fi\fi}% +\def\@UBS{\ifx\UBS\disable{}\else\ifx\UBS\enable{*}\else{l}\fi\fi}% +\def\@BULL{\ifx\BULL\disable{}\else\ifx\BULL\enable{*}\else{l}\fi\fi}% +\def\@THALES{\ifx\THALES\disable{}\else\ifx\THALES\enable{*}\else{l}\fi\fi}% +\def\@ZIED{\ifx\ZIED\disable{}\else\ifx\ZIED\enable{*}\else{l}\fi\fi}% +\begin{tabular}{|c|c|c|c|c|c|c|c|c|}\hline +\irisa & \citi & \lip & \tima & \ubs & \upmc & \bull & \thales & \zied \\\hline +\@IRISA & \@CITI & \@LIP & \@TIMA & \@UBS & \@UPMC & \@BULL & \@THALES & \@ZIED \\\hline +\end{tabular}\par +} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\newenvironment{objectif}% +{\begin{description}\item[Objectives]} +{\end{description}} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\newenvironment{workpackage}[1]% +{\newcount\wpcnt\wpcnt=0% + \def\taskname{#1}% + \begin{description}% + \let\itemsave\item% + \def\item{% + \advance\wpcnt1 + \def\wpname{\taskname-\the\wpcnt}% + \itemsave[\wpname]}} +{\end{description}} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\newenvironment{livrable}% +{% + \ifvmode\else\\\fi + \def\item##1##2##3##4##5##6{% + \gdef\name{\wpname##1}% + \\\hline + \begin{small}\textsc{\name}\end{small} & + \begin{small}\textsc{T0+##3}\end{small} & + \begin{small}\textsc{##4}\end{small} & + \begin{small}\textsc{##5}\end{small} & + } +% \begin{small} + \begin{tabular}{|c|c|c|c|p{.55\linewidth}|}\hline% + \makebox[5em]{number} & \makebox[3em]{date} & type & resp. & description +} +{\\\hline\end{tabular}% +%\end{small}\\% +} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\catcode`\@=12 +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Index: /anr/anr.tex =================================================================== --- /anr/anr.tex (revision 20) +++ /anr/anr.tex (revision 21) @@ -15,6 +15,9 @@ \geometry{verbose,a4paper,tmargin=3cm,bmargin=2cm,lmargin=2cm,rmargin=3cm} +\usepackage{anr} + %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \def\xcoach{\texttt{xcoach}\xspace} +\def\xcoachplus{\texttt{xcoach+}\xspace} \def\backbone{backbone\xspace} @@ -26,4 +29,25 @@ \definecolor{rouge}{rgb}{1.0,0.2,0.2} \def\mustbecompleted#1{} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\def\coussy{Philippe Coussy\xspace} +\def\irisa{IRI\xspace} +\def\citi{CITI\xspace} +\def\lip{LIP\xspace} +\def\tima{TIMA\xspace} +\def\ubs{UBS\xspace} % LAB-STICC +\def\upmc{LIP6\xspace} +\def\bull{BULL\xspace} +\def\thales{THALES\xspace} +\def\zied{ZIED\xspace} + +\def\alllabs{\irisa \citi \lip \tima \ubs \upmc} +\def\allcompagnies{\bull \thales \zied\xspace} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\def\ST{sub-task\xspace} +% FIXME \def\taskresponsable#1#2#3{\ifvmode\else\\\fi +% FIXME The coordinator of this task is #1 member of #2. +% FIXME The partners collaborating in this task are #3.\\} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -174,10 +198,9 @@ \end{itemize}} -\subsubsection{Task 1} +\subsubsection{Task 0} %\input{task-0} -\subsubsection{Task 2} +\subsubsection{Task 1: \textit{\backbone}} \input{task-1} - \subsection{Tasks schedule, deliverables and milestones} Index: /anr/architecture-csg.fig =================================================================== --- /anr/architecture-csg.fig (revision 20) +++ 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-630 task 2\001 -4 0 0 50 -1 2 14 0.0000 4 165 630 3960 -405 task 3\001 -4 0 0 50 -1 2 14 0.0000 4 165 630 3960 -180 task 4\001 -4 0 0 50 -1 2 14 0.0000 4 165 630 3960 45 task 5\001 -4 0 0 50 -1 2 14 0.0000 4 165 630 3960 270 task 6\001 Index: r/dependence-test.fig =================================================================== --- /anr/dependence-test.fig (revision 20) +++ (revision ) @@ -1,71 +1,0 @@ -#FIG 3.2 Produced by xfig version 3.2.5-alpha5 -Landscape -Center -Metric -Letter -100.00 -Single --2 -1200 2 -6 4635 -1575 7560 -1170 -4 1 0 50 -1 2 14 0.0000 4 165 120 4725 -1170 0\001 -4 1 0 50 -1 2 14 0.0000 4 165 120 5175 -1170 6\001 -4 1 0 50 -1 2 14 0.0000 4 165 240 5625 -1170 12\001 -4 1 0 50 -1 2 14 0.0000 4 165 240 6075 -1170 18\001 -4 1 0 50 -1 2 14 0.0000 4 165 240 6525 -1170 24\001 -4 1 0 50 -1 2 14 0.0000 4 165 240 6975 -1170 30\001 -4 1 0 50 -1 2 14 0.0000 4 165 240 7425 -1170 36\001 -4 1 0 50 -1 2 14 0.0000 4 165 675 6075 -1395 month\001 --6 -2 1 1 1 0 7 50 -1 -1 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(revision 21) +++ /anr/obsolete/dependence-task-v.fig (revision 21) @@ -0,0 +1,72 @@ +#FIG 3.2 Produced by xfig version 3.2.5 +Landscape +Center +Metric +Letter +100.00 +Single +-2 +1200 2 +6 2970 2070 3600 2520 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 2970 2070 3600 2070 3600 2520 2970 2520 2970 2070 +4 1 0 50 -1 18 16 0.0000 4 195 315 3285 2385 T3\001 +-6 +6 4050 2070 4680 2520 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 4050 2070 4680 2070 4680 2520 4050 2520 4050 2070 +4 1 0 50 -1 18 16 0.0000 4 195 315 4365 2385 T4\001 +-6 +6 3510 1170 4140 1620 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 3510 1170 4140 1170 4140 1620 3510 1620 3510 1170 +4 1 0 50 -1 18 16 0.0000 4 195 315 3825 1485 T2\001 +-6 +6 3510 270 4140 720 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 3510 270 4140 270 4140 720 3510 720 3510 270 +4 1 0 50 -1 18 16 0.0000 4 195 315 3825 585 T5\001 +-6 +6 3510 -900 4140 -450 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 3510 -900 4140 -900 4140 -450 3510 -450 3510 -900 +4 1 0 50 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120.00 + 3870 1620 3285 2070 +2 1 0 3 0 7 50 -1 -1 8.000 0 0 -1 1 0 10 + 0 0 1.00 60.00 120.00 + 3825 720 3825 765 3825 855 3825 900 3825 945 3825 990 + 3825 1035 3825 1080 3825 1125 3825 1170 +2 1 0 3 0 7 50 -1 -1 8.000 0 0 -1 1 0 2 + 0 0 1.00 60.00 120.00 + 3831 -450 3831 0 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 2025 -2475 5625 -2475 5625 4275 2025 4275 2025 -2475 +4 0 0 50 -1 18 16 0.0000 4 195 315 5175 4050 T0\001 Index: /anr/obsolete/dependence-test.fig =================================================================== --- /anr/obsolete/dependence-test.fig (revision 21) +++ /anr/obsolete/dependence-test.fig (revision 21) @@ -0,0 +1,71 @@ +#FIG 3.2 Produced by xfig version 3.2.5-alpha5 +Landscape +Center +Metric +Letter +100.00 +Single +-2 +1200 2 +6 4635 -1575 7560 -1170 +4 1 0 50 -1 2 14 0.0000 4 165 120 4725 -1170 0\001 +4 1 0 50 -1 2 14 0.0000 4 165 120 5175 -1170 6\001 +4 1 0 50 -1 2 14 0.0000 4 165 240 5625 -1170 12\001 +4 1 0 50 -1 2 14 0.0000 4 165 240 6075 -1170 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20) +++ /anr/section-1.tex (revision 21) @@ -1,88 +1,83 @@ % les objectifs globaux, -An embedded system is an application integrated into one or several chips -in order to accelerate it or to embedd it into a small device such as a -personal digital assistant (PDA). This topic is investigated since 80s -using Applications Specific Integrated Circuits (ASIC), Digital Signal -Processing (DSP) and parallel computing on multiprocessor machines or -networks. More recently, since end of 90s, other technologies appeared -like Very Large Instruction Word (VLIW), Application Specific Instruction -Processors (ASIP), System on Chip (SoC), Multi-Processors SoC (MPSoC). +A digital system is an application integrated into one or several chips. +These chips can be embedded in devices such as a personal digital assistant +(PDA), ambiant computing component, wireless sensor network (WSN). They can +also be used on a board connected to a PC to accelerate an application like +in High-Performance Computing (HPC) and in High-Speed Signal Processing (HSSP). +Digital system design has been investigated since eighties by using Applications +Specific Integrated Circuits (ASIC), Digital Signal Processing (DSP) and parallel computing on +multiprocessor machines or networks. More recently, since the end of nineties, +other technologies appeared like Very Large Instruction Word (VLIW), Application +Specific Instruction Processors (ASIP), System on Chip (SoC), Multi-Processors +SoC (MPSoC). \\ -During these last decades embedded system was reserved to major industrial -companies targeting high volume market due to the design and fabrication -costs. +During these last decades, digital systems are more and more reserved +to major companies targeting high volume market due to the design and fabrication +costs of ASIC technologies due to increasing NRE (Non Recurring-Engineering) charges. Nowadays Field Programmable Gate Arrays (FPGA), like Virtex5 from Xilinx -and Stratix4 from Altera, can implement a SoC with multiple processors and -several coprocessors for less than 10K euros per item. -In addition, High Level Synthesis (HLS) becomes more mature and allows to +and Stratix4 from Altera, can implement a complete SoC with multiple processors and +several coprocessors for less than 10K euros per device. +In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping, +Co-design, High-Level Synthesis...) become mature and allow to automate design and to drastically decrease its cost in terms of man power. -Thus, both FPGA and HLS tend to spread over HPC for small companies -targeting low volume markets. +Thus, coupling both FPGA and ESL methodologies will soon allow small and medium +enterprises (SMEs) to get into new and low-volume markets, to design highly innovative devices, +to prototype complete complex embedded systems, to realize HPC or HSSP applications. \par -To get an efficient embedded system, designer has to take into account -application characteristics when it chooses one of the former technologies. -This choice is not easy and in most cases designer has to try different -technologies to retain the most adapted one. -\\ -The first objective of COACH is to provide a framework to -design embedded system on FPGA device. -COACH framework allows designer to explore various software/hardware -partitions of the target application, to run timing and functional +The objective of COACH is to provide an environment to design emmbedded systems and +HPC applications on FPGA devices. The COACH framework will allow designer to explore various +software/hardware partitioning scenario of the target application through timing and functional simulations and to generate automatically both the software and the -synthesizable description of the hardware. -The main topics of the project are: +synthesizable description of the hardware. Exploration and design are mainly +driven by throughput, latency and/or power consumption criteria. +The main contributions of the project are: \begin{itemize} -\item Design space exploration: It consists in analysing the application -runnig on FPGA, defining the target technology (SoC, MPSoC, ASIP, ...) and -hardware/software partitioning of tasks depending on technology choice. -This exploration is driven basically by throughput, latency and power -consumption criteria. -\item Micro-architectural exploration: When hardware components are -required, the HLS tools of the framework generate them automatically. At -this stage the framework provides various HLS tools allowing the -micro-architectural space design exploration. The exploration criteria are -also throughput, latency and power consumption. -% FIXME -%CA At this stage, preliminary source-level transformations will be -%CA required to improve the efficiency of the target component. -%CA COACH will also provide such facilities, such as automatic parallelization -%CA and memory optimisation. -\item Performance measurement: For each point of design space exploration, -metrics of criteria are available such as throughput, latency, power -consumption, area, memory allocation and data locality. -They are evaluated using virtual prototyping, estimation or analysing -methodologies. -\item Targeted hardware technology: The COACH description of system is -independent of the FPGA family. -Every point of the design exploration space can be implemented on any FPGA -having the required resources. -Basically, COACH handles both Altera and Xilinx FPGA families and supports -3 generic target architectures: -the COACH architecture based on the MIPS of the TSAR ANR project and a VCI ring bus, -the Altera architecture based on the NIOS and AVALON bus, -the Xilinx architecture based on the MICROBLAZE and OPB bus. +\item Targeted hardware architecture and technology: +COACH will handle both Altera and Xilinx FPGA technologies. COACH will define +architectural templates that can be customized by additional dedicated coprocessors and ASIPs. +The parameters of the architectural templates will be the number of CPU, the operating system... +%the coprocessors, the number and the size of the FIFO communication channels +Basically, the 3 following architectural templates will be provided: +A COACH architectural template based on the MIPS of the TSAR ANR project and a VCI ring bus, +An Altera architectural template based on the NIOS and the AVALON bus, +%FIXME +% The following point has to be confirmed by XILINX +% Microblaze+OPB => ARM+Amba ??? +A Xilinx architectural template based on the MICROBLAZE and the OPB bus. +Moreover, the specification of the application will be independant of both the template +architecture and the selected technology. +\item Design space exploration: The COACH environment will allow to select and parametrize +the target architecture, to define hardware/software partitioning and to profile the application. +For each point of design space exploration, metrics such as throughput, latency, power consumption, +area, memory allocation and data locality will be provided. +This criteria will be evaluated by using virtual prototyping and high-level estimation methodologies. +\item Hardware accelerators synthesis (HAS): COACH will allow to generate automatically hardware accelerators +when required. Hence, High-Level Synthesis (HLS) tools, ASIP design environement and +source-level transformations (loop transformations and memory optimisation) will be provided. +This will allow to further explore the micro-architectural design space. \end{itemize} -As an extension of embedded system design, COACH deals also with High -Performance Computing (HPC). -In HPC, the kind of targeted application is an existing one running on PC. -COACH helps designer to accelerate it by migrating critical parts into a -SoC implemented on a FPGA plugged to the PC bus.\\ -Finally COACH will be developped under the General Public Licence for the software, -and USAGE LIBRE NON COMMERCIAL for the COACH architecture. +%In HPC, the kind of targeted application is an existing one running on PC. +%COACH helps designer to accelerate it by migrating critical parts into a +%SoC implemented on a FPGA plugged to the PC bus.\\ +%FIXME licence a speficier +The COACH environment will be designed to abstract the hardware as much as possible to the end user. +It will thus be mainly dedicated to system designers. +Finally COACH will be developped under the General Public Licence for the software tools. +and USAGE LIBRE NON COMMERCIAL for the COACH arhitecture. +%The COACH architectural templates will be freely distributed. % % verrous scientifiques et techniques \mbox{}\vspace*{.9ex}\par -System design is a very complicated task and in this project we try to simplify it -as much as possible. For this purpose we have to deal with the following scientific -and technological barriers. +System design is a very complex task this project will simplify as much as possible. +For this purpose the following scientific and technological barriers will be addressed: \begin{itemize} -\item The run frequency of the coprocessors generated by the HLS must respect -accurately the system frequency given bt the processors and bus. -\item HLS tools are sensitive to the style in which the algorithm is written -and the domain they target. The HLS tools of COACH must have a common language -and style to avoid engineering work to the designer. -\item The main problem in HPC is in the communication between the PC and the SoC -firstly at the efficiency level and secondly to eliminate enginnering effort to -implement it. +\item The clock frequency of the coprocessors generated by the HLS must respect +the frequency of the processors and the system bus. +\item HLS tools are sensitive to the coding style of the input specification +and the domain they target (control vs. data dominated). The HLS tools of COACH must have a +common language and coding style to avoid engineering work to the designer. +\item The main problem in HPC comes from timing performance and implementation of the communication +between the PC and the FPGA. +%FIXME: a completer loop tranfrom?, ASIP?, ... \end{itemize} % @@ -91,40 +86,37 @@ COACH is the result of the will of several laboratories to unify their know hows and skills in the following domains: Operating system and hardware -communication (TIMA, SITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and -HLS (LIP6, Lab-STIC and LIP). -So COACH does not starts from scratch but it relies -on SocLib~\cite{soclib} with the MUTEX and DNA/OS operating system for -system prototyping, -on BEE~\cite{bee}, GAUT~\cite{gaut08}, ROMA~\cite{roma}, SYNTOL~\cite{syntol} -and UGH~\cite{ugh08} for HLS. -The project objective is to integrate and enhance these various tools into -a unique free framework masking as much as possible these domains and its -different tools to the system designer. The main steps of this projects are: -1) Definition of the designer input as set of communicating tasks, each -task beeing described in C++ language. -2) Definition of the xhls format, an internal format for representing a -task. -3) Developping a GCC addon for generating the xhls date from a C++ task -description. -4) Adapting the existing HLS tools to read and write xhls format and -enhancing them. This allows to swap from one tool to the other and -chain them. -5) Modifying the Design System Explorator of SocLib to let the designer -to explore the design space and then to generate the bitstream to -the target FPGA. +communication (TIMA and CITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and +HLS (LIP6 and Lab-STICC) and loop tranformations (LIP). +COACH does not start from scratch but relies +on the SocLib platform~\cite{soclib} with the MUTEX and DNA/OS operating system for +SoC and MPSoC prototyping, on GAUT~\cite{gaut08} and UGH~\cite{ugh08} for HLS, on +ROMA~\cite{roma} for ASIP, on SYNTOL~\cite{syntol} and BEE~\cite{bee} for loop tranformations. +The project objective is to enhance and seamlessly integrate these tools into +a unique open source framework. +%masking these domains and its different tools to the system designer. +The main steps of this project are: +1) Definition of the user inputs: application description as set of communicating tasks, each +task beeing described in C++ language; architectural template with its parameters; design constraints. +2) Definition of the internal \xcoach format for representing a task. +3) Development of a GCC pluggin for generating the \xcoach representation of a C++ task. +4) Adaptation of the existing HLS tools to read and write the \xcoach format. This will allow to +swap from one tool to an other one and to chain them. +5) Modification of the Design System eXplorator DSX of the SocLib platform to let the user +explore the design space and then to generate the bitstream. +%FIXME : a completer \par -The role of the industrials BUL, THALES, XXX, XXX is to provide real -benchmark to guide the design of framework and prove that COACH is +The role of the industrial partners BULL, THALES, XXX is to provide real +benchmarks to guide the design of the framework and to prove that COACH is usuable and cover a large spectrum of applications. % % les retombées scientifiques, techniques et économiques \vspace*{.9ex}\par -The main scientific contributions of the project are -firstly to make high level synthesis an elementary tool of system design, -seconly to unify various synthesis techniques (same input and output formats) +The main scientific contributions of the project are: +to make high-level synthesis an elementary tool of system design, +to unify various synthesis techniques (same input and output formats) allowing the designer to swap from one to an other and even to chain them without rewritting effort, -and finally to provide a system description independent of the target -architecture and the FPGA family. +to provide a system description independent of the target architecture and +the FPGA family. \par The market of embedded system and HPC is about 4,600 M\$ today and is @@ -133,5 +125,5 @@ by major companies that can support the very high Non Recurring Engineering (NRE) costs involved in designing such system. -Small companies can only be present in this market with GPUs based solutions that have +Small and medium companies can only be present in this market with GPUs based solutions that have low NRE costs but limit the application domains.\\ COACH reduces the NRE costs to the design costs (the FPGA device being only a few @@ -142,5 +134,5 @@ that will be able to propose embedded system and accelerating solutions for standard software applications with acceptable prices.\\ -The two major FPGA companies Altera and Xilinx expect thus by supporting +The two major FPGA companies Altera and Xilinx expect this by supporting and participating in this project. Index: /anr/section-4.1.tex =================================================================== --- /anr/section-4.1.tex (revision 20) +++ /anr/section-4.1.tex (revision 21) @@ -1,9 +1,9 @@ \begin{figure}\leavevmode\center \includegraphics[width=.8\linewidth]{architecture-csg} -\caption{\label{archi-csg} software architecture for embedded system generation} +\caption{\label{archi-csg} software architecture for digital system generation} %\end{figure}\begin{figure}\leavevmode\center \mbox{}\vspace*{1ex}\\ -\includegraphics[width=.8\linewidth]{architecture-hls} -\caption{\label{archi-hls} software architecture of HLS} +\includegraphics[width=1.0\linewidth]{architecture-hls} +\caption{\label{archi-hls} software architecture of hardware accellerator synthesis} %\end{figure}\begin{figure}\leavevmode\center \mbox{}\vspace*{1ex}\\ @@ -15,49 +15,57 @@ summarize the software architecture of COACH framework we plan to develop. In figures, the dotted boxes are the softwares or formats that COACH -has to provide or define. +has to provide. \vspace*{.75ex}\par -For the system genration presented figure~\ref{archi-csg}, the conductor is -the program \verb!CSG! (COACH System Generator). Its inputs are a process -network and miscellaneaous generation parameters. -The main parameters are the template of the target hardware architecture +For the system genration presented in figure~\ref{archi-csg}, the conductor +is the tool \verb!CSG! (COACH System Generator). Its inputs are a process +network describing the application to design and the synthesis parameters. +The main parameters are the target hardware architectural template with its instanciation parameters, the hardware/software mapping of the -tasks and the FPGA device. -From these inputs \verb!CSG! can generate the system (software \& hardware) as -a SystemC simulator to prototype and explore quickly the system design -space and/or as a bitstream directly downloadable on the FPGA device. -For processing, \verb+CSG+ requires 1) a hardware template found into the -architecture library, 2) a micro-kernel, it chooses among -two in the micro kernel library, 3) the system hardware components that -are taken from the SystemC model library for the simulator and from the -VHDL component library for the FPGA bitstream. -For generating the coprocessor of a task mapped as harware, \verb+CSG+ -controls the HLS tools described below. +tasks, the FPGA device and design constraints. +\verb+CSG+ thus requires an architectural template library, a operating system +library, two system hardware component (CPU, memories, BUS...) libraries +(one for synthesis, one for simulation). +For generating the coprocessor of a task mapped as hardware, \verb+CSG+ +controls the HAS tools described below. +From these inputs \verb!CSG! can generate the entire system (both software \& +hardware) either as a SystemC simulator to prototype and explore quickly the +design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and +launch the Xilinx or Altera RTL synthesis tools.} directly downloadable on the +FPGA device. \\ -To proove CSG that COACH is open and CSG is really configurable, COACH will -basically support 3 architecture template (the COACH template based on a -MIPS processors and a VCI token ring, the Altera template based on the NIOS -and AVALON bus, the Xilinx template based on the MICROBLAZE and OPB bus) -and 2 operating systems (DNA/OS and MUTEK). Furthermore, thus is enforced -by the \mustbecompleted{FIXME:zied} contribution that consists in -implementing an other hardware target. -\\ -Finally, it is important to notice that this work is a strong -enhancement of the SocLib software. +%To proove CSG that COACH is open and CSG is really configurable, COACH will +%basically support 3 architecture template (the COACH template based on a +%MIPS processors and a VCI token ring, the Altera template based on the NIOS +%and AVALON bus, the Xilinx template based on the MICROBLAZE and OPB bus) +%and 2 operating systems (DNA/OS and MUTEK). Furthermore, thus is enforced +%by the \mustbecompleted{FIXME:zied} contribution that consists in +%implementing an other hardware target. +%\\ +%Finally, it is important to notice that this work is a strong +%enhancement of the SocLib software. \vspace*{.75ex}\par -The software architecture for HLS is presented figure~\ref{archi-hls}. -The input is a task of the process network. The HLS tools do not work +The software architecture for HAS is presented in figure~\ref{archi-hls}. +The input is a single task of the process network. The HAS tools do not work directly on the C++ task description but on an internal format called \xcoach generated by a the GNU C compiler (GCC) tainted by a COACH driver. This allows on the one hand to insure that all the tools will accept the same C++ description and on the other hand to make possible -to chain them. The front-end tools read a \xcoach description and writes -a new \xcoach description that exibits possible parallelism or implement -specific instruction for ASIP. The back-end tools read a \xcoach -description and generates a \xcoach+ description that is a \xcoach -description anotated with hardware information to let work the VHDL systemC -drivers. Furthermore, the back-end tools uses a macro-cell library. +their chaining. The front-end tools read a \xcoach description and generate +a new \xcoach description that exibits more parallelism or implement +specific instructions for ASIP. The back-end tools read a \xcoach +description and generate a \xcoachplus description. This is a \xcoach +description anotated with hardware information (scheduling, binding) required by +the VHDL and systemC drivers. +Furthermore, the back-end tools uses a macro-cell library (functional and memory +unit). \vspace*{.75ex}\par -The software architecture for HPC is presented figure~\ref{archi-hpc}. -\mustbecompleted{FIXME Miss HPC description\\\ldots\\\ldots\\\ldots\\\ldots.} +In addition to digital system design, HPC requires a supplementary +partitioning step presented in figure~\ref{archi-hpc}. The designer +splits the initial application (tag 1) in two parts: one still on the PC and the +other running in a FPGA plugged on the PCI/X PC bus. The two parts exchange data +through communication primitives (tag 2) implemented in a library. +To evaluate if the relevance of the partitioning, the designer can build a +simulator. Once the partitioning is validated, the design of the FPGA part +is done through \verb!CSG! (figure~\ref{archi-csg}). \vspace*{.75ex}\par The project is splitted into 8 tasks numbered from 0 to 7. @@ -65,41 +73,55 @@ the dissemination the other task are listed below: \begin{enumerate} -\item\textbf{\backbone:} This task groups the critical issues of the - project. They consist of the definition of COACH inputs, the \xcoach - format that is mandatory to develop the HLS tools and the HLS drivers - that are mandatory for testing the HLS tools. -\item\textbf{system generation:} This task groups \verb+CSG+s and the components - required to generate the system simulator and bitstream except the HLS - tools that belong to the task 3 and 4. These components are the - operating systems, the VHDL description and SystemC models of the - target hardware achitectures. -\item\textbf{HLS front-end:} This task groups the 4 HLS front-head. Those - are a tool that exhibits fine grain parallelism using polyedric - transformation, a tool that exhibits coarse grain parallelism, - a tool that minimizes the memory usage and a tool that implement ASIP. -\item\textbf{HLS back-end:} This task groups two HLS back-end tool, one - for treating the data oriented description, the second for treating the - control dominated description. This task contains also a the - development of a frequency adaptator that will allow the coprocessor - to respect the processor \& bus frequency. -\item\textbf{Communication software PC/FPGA-SoC:} This task groups all what is mandatorythe critical issues of the -\item\textbf{Demonstrator:} This task groups the demostrators of the COACH project. +\item\textbf{\backbone:} This task tackles the fundamental points of the + project such as the defintion of the COACH inputs and outputs, + the internal formats (e.g. \xcoach), the architectural templates and + the design flow. +\item\textbf{system generation:} This task addresses the prototyping and + the generation of digital system. Apart from HAS that belong to the task 3 + and 4, its components are those presented figure~\ref{archi-csg} + (e.g. \verb!CSG!, operating systems). +\item\textbf{HAS front-end:} This task mainly focusses on four functionalities: + optimization of the memory usage, parallelism enhancement through loop + transformations, coarse grain parallelization and ASIP generation. +\item\textbf{HAS back-end:} This task groups two functionalities: + High-Level Synthesis of data dominated description and HLS of control + dominated description. + This task contains also the development of a frequency adaptator + that will allow the coprocessors to respect the processor \& the bus + frequency. +\item\textbf{Communication between PC \& FPGA-SoC:} + This task pools the features dedicated to HPC. The main are the + partitioning validation (see figure~\ref{archi-hpc}, the sytem drivers for + both PC and FPGA-SoC sides, the hardware communication components. +\item\textbf{Demonstrator:} + This task groups the demostrators of the COACH project. + \mustbecompleted{FIXME} \end{enumerate} -This task division offers the avantage that tasks except for the "\backbone" and -"demonstrator" task are almost independent at the development level as shown -figure~\ref{dependence-dev}. The dependence at the validation level is -presented figure~\ref{dependence-test}. It is more critical but the -redundance in the tasks "HLS front-end", "HLS back-end" and "demonstrators" -reduces this inter-dependence.\\ -So if the first phasis of "\backbone" task is sucessfully conduced, most of the -projet delivrables will be carry through, even if some delivrable are lated -or missing. +% \begin{figure}\leavevmode\center -\begin{minipage}[t]{.4\linewidth} -\includegraphics[width=1\linewidth]{dependence-dev} -\caption{\label{dependence-dev}Dependence graph at development level} -\end{minipage}\hfill\begin{minipage}[t]{.4\linewidth} -\includegraphics[width=1\linewidth]{dependence-test} -\caption{\label{dependence-test}Dependence graph at validation level} -\end{minipage} +%\includegraphics[width=.4\linewidth]{dependence-task} +\includegraphics[width=0.70\linewidth]{dependence-task-h} +\caption{\label{dependence-task}Task dependencies} \end{figure} +Figure~\ref{dependence-task} presents the dependencies between the tasks. +"$task-N \longrightarrow task-M$" means that $task-N$ requires $task-M$ +to work and be demonstrated. The more bold is the arrow, the more important is +the dependency. +The graph shows: +\begin{itemize} +\item Even that $T3$ and $T4$ functionalities are complementary, their +developments are independent (thanks to \xcoach internal format). +\item $T2$ depends slightly from $T3$ and $T4$. Indeed, $T2$ may works +without $T3$ and $T4$ if we limit to digital systems without hardware +accellerators. +\item $T5$ strongly depends on $T2$ but, $T2$ does not depend at all on +$T5$. So demonstrators ($T6$) of embedded system would not be impacted if +$T5$ would fail. +\item $T1$ drives all the tasks ($T2$, $T3$, $T4$, $T5$) at the heart of +the COACH project. +\item $T7$ and $T0$ respectively depends on and impacts all the other tasks. +\end{itemize} +So this organisation offers enough robustness for insure the success of the +project except for the specification task $T1$. However, the partners meet +10 times (a one day meeting per month) during the last years to prepare the +specification and the project proposal. Index: /anr/task-1.tex =================================================================== --- /anr/task-1.tex (revision 20) +++ /anr/task-1.tex (revision 21) @@ -0,0 +1,82 @@ +%\def\TBresp{\coussy} +%\def\TBresplab{\labsticc} +%\def\TBpartner{\alllabs,\allcompagnies} + +\begin{taskinfo} +\let\UPMC\leader +\let\ALL\enable +\end{taskinfo} +% +\begin{objectif} +This task relies to the main features for embedded system. +Its objective consists of the specification of designer input, of the +definition of the hardware architectural templates and of all the features +that the HAS tools share. +\end{objectif} +% +\begin{workpackage}{T1} +\item This \ST specifies COACH for the system designer. At this + level COACH is a black box. The deliverable is a document allowing the system + designers to use COACH: feeding it (inputs), how to use it (design flow), + what COACH can generate (definition of the generic architecture of the + MPSoC and its 3 targets hardware mapping). + \begin{livrable} + \item{-1-V1}{0}{6}{d}{LIP6}{user manual} + The first milestone of the document for allowing demonstration + \ST to start. + \item{-1-V1}{6}{18}{d}{LIP6}{user manual} + The second milestone takes into account the missing features + the demonstrators rise. + \item{-1-VF}{18}{30}{d}{LIP6}{user manual} + Final release. + \end{livrable} +\item This \ST specifies the software COACH structure. The deliverable is a + document listing all the COACH software components and how they cooperate. + \begin{livrable} + \item{}{0}{6}{d}{LIP6}{decription of software architecture} + It contains the software list and the data flow among them. + \end{livrable} +\item This \ST specifies the \xcoach format. + \begin{livrable} + \item{-1-V1}{0}{6}{d x}{LIP}{specification of \xcoach format} + First release of the XML specification of the \xcoach format + and its associated documentation allowing to start HLS tools development. + \item{-1-V2}{6}{12}{d x}{LIP}{specification of \xcoach format} + Second release of XML specification of the \xcoach format + taking into account the corrections and modifications that the + developers of HLS tools rise. + \item{-1-VF}{12}{18}{d x}{LIP}{C++ to \xcoach format} + Release of XML specification of the \xcoach format enhanced with + the expression of loop potential. + \item{-2-V1}{0}{12}{x x}{\ubs}{C++ to/from \xcoach format} + The first executable generates a \xcoach description + version \taskname-3-V1 from a C++ description of a task defined in \ST + \taskname-1. + The second program regenerates a C description from a \xcoach + description. + \item{-2-VF}{12}{18}{x x}{\ubs}{C++ to/from \xcoach format} + The same programs as the former but for \xcoach format version \name-3-V2. + \item{-3-V1}{0}{18}{x}{LIP6}{\xcoach format to SystemC} + The first release of a program that translates \xcoach description to CABA + and TLM-DT SystemC. + \item{-3-VF}{18}{24}{x}{LIP6}{\xcoach format to SystemC} + The \name-3-V1 deliverable without bugs reported by the demonstrators. + \item{-4-V1}{0}{18}{x}{\ubs}{\xcoach format to VHDL} + The first release of a program that translates \xcoach description to + synthesizable VHDL description. + \item{-4-VF}{18}{24}{x}{\ubs}{\xcoach format to VHDL} + The \name-4-V1 deliverable without bugs reported by the demonstrators. + \end{livrable} +\item Backend HLS tools use a characterized macro-cell library to build the + micro-architecture of a coprocessor. The characterisation of a cell dépends + on the target device. The role of this \ST is to define the macro-cells and + to provite a tool that characterizes them automatically by synthesizing them + and by extracting their delays. This is done by using RTL synthesis. + \begin{livrable} + \item{-1-VF}{0}{6}{d}{\ubs}{macro-cell definition} + The document define the macro cell and the file format describing them. + \item{-2-VF}{0}{12}{x}{\ubs}{macro-cell library generator} + A progam that generates automatically the characterized macro-cell library + for a FPGA device. + \end{livrable} +\end{workpackage}