Changeset 234


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Timestamp:
Feb 16, 2010, 4:47:47 PM (15 years ago)
Author:
coach
Message:

Paul

File:
1 edited

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  • anr/section-1.tex

    r169 r234  
    1414implement a complete MPSoC with multiple processors and several dedicated
    1515coprocessors for a few Keuros per device. Many applications are initially captured
    16 algorithmically in High-Level Languages HLLs such as C/C++. This has led to growing interest
     16algorithmically in High-Level Languages (HLLs) such as C/C++. This has led to growing interest
    1717in tools that can provide an implementation path directly from HLLs to hardware.
    1818Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
     
    7171    However, the specification of the application will be independant of both the
    7272    architectural template and the target FPGA device.
    73     Basically, the 3 following architectural templates will be provided:
     73    Basically, the following three architectural templates will be provided:
    7474    \begin{enumerate}
    7575    \item A \mustbecompleted{FIXME :: Neutral est tres pejoratif. Technology inependent, independant, standard ???} Neutral architectural template based on the SoCLib IP core library and the
     
    105105\\
    106106The COACH project does not start from scratch.
    107 It stronly relies on the SoCLib virtual prototyping platform~\cite{soclib} for prototyping,
    108 
    109 (DSX, component library), operating systems (MUTEKH, DNA/OS).
     107It stronly relies on the SoCLib virtual prototyping platform~\cite{soclib} for prototyping, (DSX, component library), operating systems (MUTEKH, DNA/OS).
    110108It also leverages on  several existing technologies:
    111109on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS,
     
    113111on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and transformations
    114112and on the \xilinx and \altera IP core libraries.
    115 Finally it will use the \xilinx and \altera logic and phisical synthesis tools to generate the FPGA configuration
     113Finally it will use the \xilinx and \altera logic and physical synthesis tools to generate the FPGA configuration
    116114bitstreams.
    117115\parlf
     
    150148The role of the industrial partners \bull, \thales, \navtel and \zied is to provide
    151149real use cases to benchmark the COACH design environment and to analyze the designer productivity
    152 imrovments. \mustbecompleted{FIXME :: j'ai ajoute "and to analyze..." OK ?} \mustbecompleted{FIXME :: FlexRAS
     150improvements. \mustbecompleted{FIXME :: j'ai ajoute "and to analyze..." OK ?} \mustbecompleted{FIXME :: FlexRAS
    153151sont fournisseur de techno et non de uses cases no ???}
    154152\parlf
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