Index: /anr/section-1.tex
===================================================================
--- /anr/section-1.tex	(revision 233)
+++ /anr/section-1.tex	(revision 234)
@@ -14,5 +14,5 @@
 implement a complete MPSoC with multiple processors and several dedicated
 coprocessors for a few Keuros per device. Many applications are initially captured 
-algorithmically in High-Level Languages HLLs such as C/C++. This has led to growing interest 
+algorithmically in High-Level Languages (HLLs) such as C/C++. This has led to growing interest 
 in tools that can provide an implementation path directly from HLLs to hardware. 
 Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
@@ -71,5 +71,5 @@
     However, the specification of the application will be independant of both the
     architectural template and the target FPGA device.
-    Basically, the 3 following architectural templates will be provided:
+    Basically, the following three architectural templates will be provided:
     \begin{enumerate}
     \item A \mustbecompleted{FIXME :: Neutral est tres pejoratif. Technology inependent, independant, standard ???} Neutral architectural template based on the SoCLib IP core library and the
@@ -105,7 +105,5 @@
 \\
 The COACH project does not start from scratch.
-It stronly relies on the SoCLib virtual prototyping platform~\cite{soclib} for prototyping,
-
-(DSX, component library), operating systems (MUTEKH, DNA/OS).
+It stronly relies on the SoCLib virtual prototyping platform~\cite{soclib} for prototyping, (DSX, component library), operating systems (MUTEKH, DNA/OS).
 It also leverages on  several existing technologies:
 on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS, 
@@ -113,5 +111,5 @@
 on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and transformations
 and on the \xilinx and \altera IP core libraries.
-Finally it will use the \xilinx and \altera logic and phisical synthesis tools to generate the FPGA configuration
+Finally it will use the \xilinx and \altera logic and physical synthesis tools to generate the FPGA configuration
 bitstreams.
 \parlf
@@ -150,5 +148,5 @@
 The role of the industrial partners \bull, \thales, \navtel and \zied is to provide
 real use cases to benchmark the COACH design environment and to analyze the designer productivity 
-imrovments. \mustbecompleted{FIXME :: j'ai ajoute "and to analyze..." OK ?} \mustbecompleted{FIXME :: FlexRAS
+improvements. \mustbecompleted{FIXME :: j'ai ajoute "and to analyze..." OK ?} \mustbecompleted{FIXME :: FlexRAS
 sont fournisseur de techno et non de uses cases no ???}
 \parlf