Index: /anr/section-3.1.tex =================================================================== --- /anr/section-3.1.tex (revision 234) +++ /anr/section-3.1.tex (revision 235) @@ -99,7 +99,7 @@ Moreover, low power consumption constraint is mandatory for embedded systems. However, it is not yet well handled or not handle at all by the synthesis tools already available, -\item The parallelism is extracted from initial algorithmic specification, +\item The parallelism is extracted from initial algorithmic specification. To get more parallelism or to reduce the amount of required memory in the SoC, the user -must re-write the algorithmic specification while there is techniques as polyedric +must re-write the algorithmic specification while there is techniques such as polyedric transformations to increase the intrinsic parallelism, \item While they support limited loop transformations like loop unrolling and loop Index: /anr/section-3.2.tex =================================================================== --- /anr/section-3.2.tex (revision 234) +++ /anr/section-3.2.tex (revision 235) @@ -11,14 +11,16 @@ \item[HPC setup:] During this step, the user splits the application into 2 parts: the host application which remains on a PC and the SoC application which is mapped on the FPGA. -The COACH framework will provide a SystemC simulation model of the whole system (PC+communication+FPGA-SoC) which will allow performance evaluation of the partitioning. +COACH will allow to automatically translate high level language programs to FPGA configurations. +In addition, it will provide a SystemC simulation model of the whole system (PC+communication+FPGA-SoC) +which will allow performance evaluation of the partitioning. \item[SoC design:] In this phase, -the user will be able to obtain simulators for the SoC at different abstraction levels by giving to the COACH framework a SoC description. -This description will consist of a process network corresponding to the SoC application, +COACH will allow the user to obtain simulators for the SoC at different abstraction levels by giving to the COACH framework a SoC description. +This description will consist of a process network corresponding to the application, an OS, an instance of a generic hardware platform -and a mapping of processes on the platform components. The supported mapping are +and a mapping of processes on the platform components. COACH will offer different targets to map the processes: software (the process runs on a SoC processor), ASIP (the process runs on a SoC processor enhanced with dedicated instructions), and hardware (the process runs into a coprocessor that is generated by HLS and plugged on the SoC bus). -\item[Application compilation:] Once the SoC description is validated, COACH will generate automatically +\item[Application compilation:] Once the SoC description is validated through performances analysis, COACH will generate automatically an FPGA bitstream containing the hardware platform with the SoC application software and an executable containing the host application. The user will be able to launch the application by @@ -39,7 +41,54 @@ % Detailler les verrous scientifiques et techniques a lever par la realisation du projet. -System design is a very complicated task and in this project we will try to simplify it -as much as possible. For this purpose we have to deal with the following scientific -and technological barriers. +System design is a very complex task and in this project we will try to simplify it +as much as possible. For this purpose the following scientific and technological barriers +have to be addressed. + +\begin{description} +\item[Design Space Exploration:] + The COACH environment will allow to easily map an application described by using a process + network Model of Computation (MoC) on a shared-memory, MPSoC architecture. COACH will + allow to explore the design space by allowing system designer to select and + parameterize the target architecture, and to define the best hardware/software + partitioning of the application. +\item[Hardware Accelerators Synthesis (HAS):] + COACH will allow the automatic generation of hardware accelerators when required. + Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor + (ASIP) design environment and source-level transformation tools (loop transformations + and memory optimisation) will be provided. + This will allow further exploration of the micro-architectural design space. + HLS tools are sensitive to the coding style of the input specification and the domain + they target (control vs. data dominated). + The HLS tools of COACH will support a common language and coding style to avoid + re-engineering by the designer. +\item[Platform based design:] + COACH will handle both \altera and \xilinx FPGA devices. + COACH will define architectural templates that can be customized by adding + dedicated coprocessors and ASIPs and by fixing template parameters such as + the number of embedded processors, the number of sizes of embedded memory banks + or the embedded the operating system. + However, the specification of the application will be independant of both the + architectural template and the target FPGA device. + Basically, the 3 following architectural templates will be provided: + \begin{enumerate} + \item A \mustbecompleted{FIXME :: Neutral est tres pejoratif. Technology inependent, independant, standard ???} Neutral architectural template based on the SoCLib IP core library and the + VCI/OCP communication infrastructure. + \item An \altera architectural template based on the \altera IP core library, the + AVALON system bus and the NIOS processor. + \item A \xilinx architectural template based on the Xilinx IP core library, the PLB + system bus and the Microblaze processor. + \end{enumerate} +\item[Hardware/Software communication middleware:] + COACH will implement an homogeneous HW/SW communication infrastructure and + communication APIs (Application Programming Interface), that will be used for + communications between software tasks running on embedded processors and + dedicated hardware coprocessors. +\end{description} + + + +---------------------------------------------------------------------------------------------- + + \begin{itemize} \item HLS tools are sensitive to the style in which the algorithm is written. @@ -83,7 +132,7 @@ 3 architectural templates that are synthesizable and that can be prototyped, one design space exploration tool, -2 operating systems (DNA/OS and MUTEKH. +2 operating systems (DNA/OS and MUTEKH). \\ The framework fonctionality will be demonstrated with the demonstrators (see task-7 page~\pageref{task-7}) and the tutorial example (see task-8 -page~\ref{subtask-tutorial}. +page~\ref{subtask-tutorial}).