Index: /anr/section-2.1.tex
===================================================================
--- /anr/section-2.1.tex	(revision 236)
+++ /anr/section-2.1.tex	(revision 237)
@@ -42,5 +42,5 @@
 on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement
 complex systems like multi-processors platform with application dedicated coprocessors. 
-Table~\ref{fpga_market} shows the estimation of FPGA worldwide market in the next years in
+Table~\ref{fpga_market} shows the estimation of the FPGA worldwide market in the next years in
 various application domains. The ``high end'' lines concern only FPGA with high logic
 capacity for complex system implementations.
Index: /anr/section-2.2.tex
===================================================================
--- /anr/section-2.2.tex	(revision 236)
+++ /anr/section-2.2.tex	(revision 237)
@@ -52,9 +52,9 @@
     for FPGA synthesis.
   \item[ROMA] The ROMA ANR project \cite{roma}
-    involving IRISA (CAIRN team), LIRMM, CEA List THOMSON France R\&D,
+    involving IRISA (CAIRN team), LIRMM, CEA List, THOMSON France R\&D,
     proposes to develop a reconfigurable processor, exhibiting high
     silicon density and power efficiency, able to adapt its computing
     structure to computation patterns that can be speed-up and/or
-    power efficient.  The ROMA project study a pipeline-based of
+    power efficient.  The ROMA project study a pipeline of
     evolved low-power coarse grain reconfigurable operators to avoid
     traditional overhead, in reconfigurable devices, related to the
@@ -66,5 +66,5 @@
 %    ASIP processors.
   \item[TSAR]
-     The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and the \upmc targets the design of a 
+     The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and \upmc targets the design of a 
 %    The TSAR MEDEA+ project (2008-2010) targets the design of a 
     scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib
@@ -118,5 +118,5 @@
 COACH will address new embedded systems architectures by allowing the design of 
 Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design 
-constraints and objectives (real-time, low-power). It will permit to design  complex SoC 
+constraints and objectives (real-time, low-power). It will permit designing  complex SoC 
 based on IP cores (memory, peripherals, network controllers, communication processors), 
 running Embedded Software, as well as an Operating System with associated middleware and 
@@ -126,5 +126,5 @@
 %
 \item[Axis 2] \textit{Infrastructures pour l'Internet, le calcul intensif ou les services} \\
-COACH will address High-Performance Computing (HPC) by helping designer to accelerate an 
+COACH will address High-Performance Computing (HPC) by helping designers to accelerate an 
 application running on a PC by migrating critical parts into a SoC implemented on an FPGA 
 plugged to the PC bus (through a communication link like PCI/X). COACH will reduce the designer 
Index: /anr/section-2.tex
===================================================================
--- /anr/section-2.tex	(revision 236)
+++ /anr/section-2.tex	(revision 237)
@@ -1,3 +1,3 @@
-Embedded systems (SoC and MPSoC) became an inevitable evolution in microelectronic industry.
+Embedded systems (SoC and MPSoC) became an inevitable evolution in the microelectronic industry.
 Due to the exploding fabrication costs, the ASIC technology (Application Specific Integrated Circuit) 
 is not an option for SMEs (Small and Medium Enterprises).
@@ -21,5 +21,5 @@
 The COACH project will leverage on the expertise gained in the field of virtual prototyping
 with the SoCLib platform, to propose a new design flow based on a small number of architectural templates.
-An architectural template is a generic, parametrized architecture, relying on a predefined library 
+An architectural template is a generic, parameterized architecture, relying on a predefined library 
 of IP cores. 
 Besides using a specific collection of general purpose IP cores (such as processors cores,
Index: /anr/section-3.1.tex
===================================================================
--- /anr/section-3.1.tex	(revision 236)
+++ /anr/section-3.1.tex	(revision 237)
@@ -8,7 +8,7 @@
 \subsubsection{High Performance Computing}
 % Un marché bouffé par les archi GPGPU tel que le FERMI de NvidiaCUDA programming language
-High-Performance Computing (HPC) world is composed of three main families of architectures:
+The High-Performance Computing (HPC) world is composed of three main families of architectures:
 many-core, GPGPU (General Purpose computation on Graphics Unit Processing) and FPGA.
-The two first families are dominating the market by taking benefit 
+The first  two families are dominating the market by taking benefit 
 of the strength and influence of mass-market leaders (Intel, Nvidia).
 %such as Intel for many-core CPU and Nvidia for GPGPU.
@@ -51,5 +51,5 @@
 \subsubsection{System Synthesis}
 Today, several solutions for system design are proposed and commercialized.
-The existing commercial or free tools does not
+The existing commercial or free tools do not
 cover the whole system synthesis process in a full automatic way. Moreover,
 they are bound to a particular device family and to IPs library.
@@ -84,8 +84,8 @@
 set of constraints (area, power, frequency, ...) to a micro-architecture at
 Register Transfer Level (RTL).
-Several academic and commercial tools are today available. Most common
+Several academic and commercial tools are today available. The most common
 tools are SPARK~\cite{spark04}, GAUT~\cite{gaut08}, UGH~\cite{ugh08} in the
 academic world and CATAPULTC~\cite{catapult-c}, PICO~\cite{pico} and
-CYNTHETIZER~\cite{cynthetizer} in commercial world.  Despite their
+CYNTHETIZER~\cite{cynthetizer} in the commercial world.  Despite their
 maturity, their usage is restrained by \cite{IEEEDT} \cite{CATRENE} \cite{HLSBOOK}:
 \begin{itemize}
@@ -98,5 +98,5 @@
 designs are multi-constrained, 
 Moreover, low power consumption constraint is mandatory for embedded systems. 
-However, it is not yet well handled or not handle at all by the synthesis tools already available,
+However, it is not yet well handled or not handled at all by the synthesis tools already available,
 \item The parallelism is extracted from initial algorithmic specification.
 To get more parallelism or to reduce the amount of required memory in the SoC, the user
@@ -106,10 +106,10 @@
 pipelining, current HLS tools do not provide support for design space exploration neither
 through automatic loop transformations nor through memory mapping,
-\item Despite they have the same input language (C/C++), they are sensitive to the style in
-which the algorithm is written. Consequently, engineering work is required to swap from 
+\item Despite having the same input language (C/C++), they are sensitive to the style in
+which the algorithm dis written. Consequently, engineering work is required to swap from 
 a tool to another,
 \item They do not respect accurately the frequency constraint when they target an FPGA device.
 Their error is about 10 percent. This is annoying when the generated component is integrated
-in a SoC since it will slow down the hole system.
+in a SoC since it will slow down the whole system.
 \end{itemize}
 Regarding these limitations, it is necessary to create a new tool generation reducing the gap 
Index: /anr/section-3.2.tex
===================================================================
--- /anr/section-3.2.tex	(revision 236)
+++ /anr/section-3.2.tex	(revision 237)
@@ -113,5 +113,5 @@
 the required performance of a coprocessor (clock frequency, maximum cycles for
 a given computation, power consumption, etc) are imposed by the other system
-components. The challenge is to allow user to control accurately the synthesis
+components. The challenge is to allow the user to control accurately the synthesis
 process. For instance, the clock frequency must not be a result of the RTL synthesis
 but a strict synthesis constraint.
Index: /anr/section-4.1.tex
===================================================================
--- /anr/section-4.1.tex	(revision 236)
+++ /anr/section-4.1.tex	(revision 237)
@@ -60,6 +60,6 @@
 is done through \verb!CSG! (figure~\ref{archi-csg}).
 \parlf
-The project is split into 8 tasks numbered from 1 to 8. There are described
-below and detailled in section \ref{task-description}.
+The project is split into 8 tasks numbered from 1 to 8. They are described
+in short below and in detail in section \ref{task-description}.
 \begin{description}
 \item[Task-1: \textit{Project management}]
Index: /anr/section-5.tex
===================================================================
--- /anr/section-5.tex	(revision 236)
+++ /anr/section-5.tex	(revision 237)
@@ -2,5 +2,5 @@
 
 The COACH project will bring new scientific results in various fields, such as high level synthesis,
-hardware/software codesign, virtual prototyping, harware oriented compilation techniques,
+hardware/software codesign, virtual prototyping, hardware oriented compilation techniques,
 automatic parallelisation, etc. These results will be published in relevant International
 Conferences, namely DATE, DAC, or ICCAD. 
@@ -15,5 +15,5 @@
 
 Following the general policy of the SoCLib platform, the COACH project will be an 
-open infrastructure, and the COACH tools and libraries will available in the framework 
+open infrastructure, and the COACH tools and libraries will be available in the framework 
 of the SoCLib WEB server. This server will be maintened by the UPMC/LIP6 laboratory. 
 
Index: /anr/task-0.tex
===================================================================
--- /anr/task-0.tex	(revision 236)
+++ /anr/task-0.tex	(revision 237)
@@ -32,7 +32,7 @@
         Global management of the project at all the
         levels: progress monitoring, record keeping, meeting organization, review
-        organization, the writting of the review reports.
+        organization, the writing of the review reports.
     \end{livrable}
-  \subtask This \ST consists managing the project at the partner level.
+  \subtask This \ST consists in managing the project at the partner level.
     It includes mainly the progress monitoring, the record keeping the participation to the
     project meetings and the communication with the project leader and the other partners.
Index: /anr/task-1.tex
===================================================================
--- /anr/task-1.tex	(revision 236)
+++ /anr/task-1.tex	(revision 237)
@@ -109,5 +109,5 @@
         \setMacroInAuxFile{specXilinxOptimization}
         This deliverable consists in optimizing the VHDL generated from \xcoachplus format
-        (deliverable \novers{\specXcoachToVhdl}) to the \xilinx RTL synthesis tools.
+        (deliverable \novers{\specXcoachToVhdl}) for the \xilinx RTL synthesis tools.
         \ubs will provide several examples of VHDL source files generated from \xcoachplus,
         with explanations about generation process of main data structures used in VHDL sources, 
Index: /anr/task-2.tex
===================================================================
--- /anr/task-2.tex	(revision 236)
+++ /anr/task-2.tex	(revision 237)
@@ -11,5 +11,5 @@
 Its is described on figure~\ref{archi-csg}.
 Its objective is to allow the system designer to explore the design space by
-quickly prototyping and then to automatically generate the FPGA-SoC system.
+quickly prototyping and then to automatically generate the FPGA-SoC systems.
 This task consists of
 \begin{itemize}
@@ -23,5 +23,5 @@
 This task being based on the SoCLib platform, a first release will be delivered at $T0+12$
 to allow the demonstrators to start working.
-This release will include the standard communication schemes (base on SoCLib MWMR component)
+This release will include the standard communication schemes (based on SoCLib MWMR component)
 and support the neutral architectural template for prototyping and hardware generation.
 \end{objectif}
Index: /anr/task-3.tex
===================================================================
--- /anr/task-3.tex	(revision 236)
+++ /anr/task-3.tex	(revision 237)
@@ -63,5 +63,5 @@
    \begin{livrable}
     \itemV{0}{6}{d}{\Slip}{Method, Preliminary Definition}
-      Description and specification work construction method for programs with 
+      Description and specification of a process construction method for programs with 
       polyhedral loops. 
     \itemL{30}{36}{d}{\Slip}{Process generation method}{10:0:9}
Index: /anr/task-5.tex
===================================================================
--- /anr/task-5.tex	(revision 236)
+++ /anr/task-5.tex	(revision 237)
@@ -25,5 +25,5 @@
 
 The low level hardware transmission support will be the PCI/X bus which allows high bit-rate
-transfers. The reasons of this choices are that both \altera and \xilinx provide PCI/X IP for
+transfers. The reasons of this choice are that both \altera and \xilinx provide PCI/X IP for
 their FPGA and that GPU HPC softwares use also it.
 %This will allow us at least to be inspired by GPU communication schemes and may be to reuse
@@ -90,7 +90,7 @@
     \begin{livrable}
     \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2}
-        Modification of CSG software to support statically reconfigurable task.
+        Modification of the CSG software to support statically reconfigurable tasks.
     \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:4:12}
-		This livrable is a CSG module allowing to partition the task graph on
+		This livrable is a CSG module allowing to partition the task graph along
 		the dynamic partial reconfiguration regions. The resulting task-region assignement
 		is directly used for generation of bitstreams. The module also produces reconfiguration
Index: /anr/task-7.tex
===================================================================
--- /anr/task-7.tex	(revision 236)
+++ /anr/task-7.tex	(revision 237)
@@ -5,5 +5,5 @@
 %
 \begin{objectif}
-This task relies to the diffusion of the project results.
+This task relates to the diffusion of the project results.
 The objective is to ensure the COACH dissemination by publishing on a public WEB site all
 the information that a COACH user requires.
@@ -20,5 +20,5 @@
 %
 \begin{workpackage}
-  \subtask This \ST relies to the management of the WEB site and to the distribution of
+  \subtask This \ST relates to the management of the WEB site and to the distribution of
     the COACH releases.
     \begin{livrable}