Changeset 238 for anr


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Timestamp:
Feb 16, 2010, 5:38:52 PM (15 years ago)
Author:
coach
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UBS

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  • anr/section-3.2.tex

    r237 r238  
    4949    The COACH environment will allow to easily map an application described by using a process
    5050        network Model of Computation (MoC) on a shared-memory, MPSoC architecture. COACH will
    51         allow to explore the design space by allowing system designer to select and
     51        permit to explore the design space by allowing system designer to select and
    5252        parameterize the target architecture, and to define the best hardware/software
    5353        partitioning of the application.
    54 \item[Hardware Accelerators Synthesis (HAS):]
    55     COACH will allow the automatic generation of hardware accelerators when required.
    56     Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor
    57     (ASIP) design environment and source-level transformation tools (loop transformations
    58     and memory optimisation) will be provided.
    59     This will allow further exploration of the micro-architectural design space.
    60     HLS tools are sensitive to the coding style of the input specification and the domain
    61     they target (control vs. data dominated).
    62     The HLS tools of COACH will support a common language and coding style to avoid
    63     re-engineering by the designer.
     54
     55\item[High-Level Synthesis:]
     56    COACH will allow the automatic generation of hardware accelerators when required
     57        by using High-Level Synthesis (HLS) tools.
     58        HLS will thus be fully integrated into a complete system-level design environment.
     59        Moreover, COACH will support both data and control dominated applications.
     60    Indeed, the HLS tools of COACH will support a common language and coding style
     61        to avoid re-engineering by the designer.
     62    COACH will provide a tool which will automatically explore the micro-architectural
     63        design space of coprocessor.
     64
     65\item[High-level code transformation:]
     66    COACH will allow to optimize the memory usage, to enhance the parallelism through
     67        loop transformations and parallelization. The challenge is to identify the coarse
     68        grained parallelism and to generate,
     69        from a sequential algorithm, application containing multiple communicating
     70        tasks. To this aim, one may adapt techniques which were developed in the 1990 for
     71        the construction of distributed programs. However, in the context of HLS, there are
     72        still several original problems to be solved, mainly to do with the construction of
     73        FIFO communication channels and with memory optimization.
     74        Additionnal preprocessing, source-level transformations, are thus
     75        required to improve the process.
     76        Particularly, this includes parallelism exposure and efficient memory mapping.
     77        COACH will support code transformation by providing a source to source C2C tool.
     78
    6479\item[Platform based design:]
    65     COACH will handle both \altera and \xilinx FPGA devices.
    6680    COACH will define architectural templates that can be customized by adding
    6781    dedicated coprocessors and ASIPs and by fixing template parameters such as
    … …  
    7084    However, the specification of the application will be independant of both the
    7185    architectural template and the target FPGA device.
    72     Basically, the 3 following architectural templates will be provided:
    73     \begin{enumerate}
    74     \item A \mustbecompleted{FIXME :: Neutral est tres pejoratif. Technology inependent, independant, standard ???} Neutral architectural template based on the SoCLib IP core library and the
    75       VCI/OCP communication infrastructure.
    76     \item An \altera architectural template based on the \altera IP core library, the
    77       AVALON system bus and the NIOS processor.
    78     \item A \xilinx architectural template based on the Xilinx IP core library, the PLB
    79       system bus and the Microblaze processor.
    80     \end{enumerate}
     86
    8187\item[Hardware/Software communication middleware:]
    8288    COACH will implement an homogeneous HW/SW communication infrastructure and
    8389    communication APIs (Application Programming Interface), that will be used for
    8490    communications between software tasks running on embedded processors and
    85     dedicated hardware coprocessors.
     91    dedicated hardware coprocessors. This will allow explore the design space by
     92        mapping the tasks of application (described as a process network) on a
     93        shared-memory, MPSoC architecture.
     94
     95\item[Processor customization:]
     96ASIP design will be addressed by the COACH project. COACH will allow system designers to explore
     97the various level of interactions between the original CPU micro-architecture and its
     98  extension. It will also allow to retarget the compiler instruction-selection pass. Finally,
     99 COACH will integrate ASIP design in a complete System-level design framework.
     100
     101\item [High-Performance Computing:] The main problem in HPC is the communication
     102between the PC and the SoC. This problem has 2 aspects. The first one is the run-time
     103efficiency. The second is its engineering  cost, especially if one want to refine an
     104implementation at several abstract levels.
     105COACH will
     106
     107%\item The COACH design flow has a top-down approach. In such a case,
     108%the required performance of a coprocessor (clock frequency, maximum cycles for
     109%a given computation, power consumption, etc) are imposed by the other system
     110%components. The challenge is to allow the user to control accurately the synthesis
     111%process. For instance, the clock frequency must not be a result of the RTL synthesis
     112%but a strict synthesis constraint.
     113
    86114\end{description}
    87115
    88116
    89117
    90 ----------------------------------------------------------------------------------------------
    91 
    92 
    93 \begin{itemize}
    94 \item HLS tools are sensitive to the style in which the algorithm is written.
    95 In addition, they are are not integrated into an architecture and system
    96 exploration tool. Consequently, engineering work is required to swap from a tool to another,
    97 to integrate the resulting simulation model to an architectural exploration tool
    98 and to synthesize the generated RTL description.
    99 %CA Additionnal preprocessing, source-level transformations, are thus
    100 %CA required to improve the process.
    101 %CA Particularly, this includes parallelism exposure and efficient memory mapping.
    102 \item Most HLS tools translate a sequential algorithm into a coprocessor
    103 containing a single data-path and finite state machine (FSM). In this way,
    104 only the fine grained parallelism is exploited (ILP parallelism).
    105 The challenge is to identify the coarse grained parallelism and to generate,
    106 from a sequential algorithm, coprocessor containing multiple communicating
    107 tasks (data-paths and FSMs). To this aim, one may adapt techniques which
    108 were developed in the 1990 for the construction of distributed programs.
    109 However, in the context of HLS, there are still several original problems
    110 to be solved, mainly to do with the construction of FIFO communication
    111 channels and with memory optimization.
    112 \item The COACH design flow has a top-down approach. In such a case,
    113 the required performance of a coprocessor (clock frequency, maximum cycles for
    114 a given computation, power consumption, etc) are imposed by the other system
    115 components. The challenge is to allow the user to control accurately the synthesis
    116 process. For instance, the clock frequency must not be a result of the RTL synthesis
    117 but a strict synthesis constraint.
    118 \item The main problem in HPC is the communication between the PC and the SoC.
    119 This problem has 2 aspects. The first one is the run-time efficiency. The second is
    120 its engineering  cost, especially if one want to refine an implementation
    121 at several abstract levels.
    122 
    123 \end{itemize}
    124118
    125119%Presenter les resultats escomptes en proposant si possible des criteres de reussite
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