Index: /anr/section-3.2.tex =================================================================== --- /anr/section-3.2.tex (revision 237) +++ /anr/section-3.2.tex (revision 238) @@ -49,19 +49,33 @@ The COACH environment will allow to easily map an application described by using a process network Model of Computation (MoC) on a shared-memory, MPSoC architecture. COACH will - allow to explore the design space by allowing system designer to select and + permit to explore the design space by allowing system designer to select and parameterize the target architecture, and to define the best hardware/software partitioning of the application. -\item[Hardware Accelerators Synthesis (HAS):] - COACH will allow the automatic generation of hardware accelerators when required. - Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor - (ASIP) design environment and source-level transformation tools (loop transformations - and memory optimisation) will be provided. - This will allow further exploration of the micro-architectural design space. - HLS tools are sensitive to the coding style of the input specification and the domain - they target (control vs. data dominated). - The HLS tools of COACH will support a common language and coding style to avoid - re-engineering by the designer. + +\item[High-Level Synthesis:] + COACH will allow the automatic generation of hardware accelerators when required + by using High-Level Synthesis (HLS) tools. + HLS will thus be fully integrated into a complete system-level design environment. + Moreover, COACH will support both data and control dominated applications. + Indeed, the HLS tools of COACH will support a common language and coding style + to avoid re-engineering by the designer. + COACH will provide a tool which will automatically explore the micro-architectural + design space of coprocessor. + +\item[High-level code transformation:] + COACH will allow to optimize the memory usage, to enhance the parallelism through + loop transformations and parallelization. The challenge is to identify the coarse + grained parallelism and to generate, + from a sequential algorithm, application containing multiple communicating + tasks. To this aim, one may adapt techniques which were developed in the 1990 for + the construction of distributed programs. However, in the context of HLS, there are + still several original problems to be solved, mainly to do with the construction of + FIFO communication channels and with memory optimization. + Additionnal preprocessing, source-level transformations, are thus + required to improve the process. + Particularly, this includes parallelism exposure and efficient memory mapping. + COACH will support code transformation by providing a source to source C2C tool. + \item[Platform based design:] - COACH will handle both \altera and \xilinx FPGA devices. COACH will define architectural templates that can be customized by adding dedicated coprocessors and ASIPs and by fixing template parameters such as @@ -70,56 +84,36 @@ However, the specification of the application will be independant of both the architectural template and the target FPGA device. - Basically, the 3 following architectural templates will be provided: - \begin{enumerate} - \item A \mustbecompleted{FIXME :: Neutral est tres pejoratif. Technology inependent, independant, standard ???} Neutral architectural template based on the SoCLib IP core library and the - VCI/OCP communication infrastructure. - \item An \altera architectural template based on the \altera IP core library, the - AVALON system bus and the NIOS processor. - \item A \xilinx architectural template based on the Xilinx IP core library, the PLB - system bus and the Microblaze processor. - \end{enumerate} + \item[Hardware/Software communication middleware:] COACH will implement an homogeneous HW/SW communication infrastructure and communication APIs (Application Programming Interface), that will be used for communications between software tasks running on embedded processors and - dedicated hardware coprocessors. + dedicated hardware coprocessors. This will allow explore the design space by + mapping the tasks of application (described as a process network) on a + shared-memory, MPSoC architecture. + +\item[Processor customization:] +ASIP design will be addressed by the COACH project. COACH will allow system designers to explore +the various level of interactions between the original CPU micro-architecture and its + extension. It will also allow to retarget the compiler instruction-selection pass. Finally, + COACH will integrate ASIP design in a complete System-level design framework. + +\item [High-Performance Computing:] The main problem in HPC is the communication +between the PC and the SoC. This problem has 2 aspects. The first one is the run-time +efficiency. The second is its engineering cost, especially if one want to refine an +implementation at several abstract levels. +COACH will + +%\item The COACH design flow has a top-down approach. In such a case, +%the required performance of a coprocessor (clock frequency, maximum cycles for +%a given computation, power consumption, etc) are imposed by the other system +%components. The challenge is to allow the user to control accurately the synthesis +%process. For instance, the clock frequency must not be a result of the RTL synthesis +%but a strict synthesis constraint. + \end{description} ----------------------------------------------------------------------------------------------- - - -\begin{itemize} -\item HLS tools are sensitive to the style in which the algorithm is written. -In addition, they are are not integrated into an architecture and system -exploration tool. Consequently, engineering work is required to swap from a tool to another, -to integrate the resulting simulation model to an architectural exploration tool -and to synthesize the generated RTL description. -%CA Additionnal preprocessing, source-level transformations, are thus -%CA required to improve the process. -%CA Particularly, this includes parallelism exposure and efficient memory mapping. -\item Most HLS tools translate a sequential algorithm into a coprocessor -containing a single data-path and finite state machine (FSM). In this way, -only the fine grained parallelism is exploited (ILP parallelism). -The challenge is to identify the coarse grained parallelism and to generate, -from a sequential algorithm, coprocessor containing multiple communicating -tasks (data-paths and FSMs). To this aim, one may adapt techniques which -were developed in the 1990 for the construction of distributed programs. -However, in the context of HLS, there are still several original problems -to be solved, mainly to do with the construction of FIFO communication -channels and with memory optimization. -\item The COACH design flow has a top-down approach. In such a case, -the required performance of a coprocessor (clock frequency, maximum cycles for -a given computation, power consumption, etc) are imposed by the other system -components. The challenge is to allow the user to control accurately the synthesis -process. For instance, the clock frequency must not be a result of the RTL synthesis -but a strict synthesis constraint. -\item The main problem in HPC is the communication between the PC and the SoC. -This problem has 2 aspects. The first one is the run-time efficiency. The second is -its engineering cost, especially if one want to refine an implementation -at several abstract levels. - -\end{itemize} %Presenter les resultats escomptes en proposant si possible des criteres de reussite