Index: /anr/anr.tex =================================================================== --- /anr/anr.tex (revision 22) +++ /anr/anr.tex (revision 23) @@ -38,4 +38,6 @@ \def\ubs{UBS\xspace} % LAB-STICC \def\upmc{LIP6\xspace} +\def\altera{ALTERA\xspace} +\def\xilinx{XILINX\xspace} \def\bull{BULL\xspace} \def\thales{THALES\xspace} @@ -203,4 +205,19 @@ \subsubsection{Task 1: \textit{\backbone}} \input{task-1} + +\subsubsection{Task 2: \textit{system generation}} +\input{task-2} + +\subsubsection{Task 3: \textit{HAS front-end}} +%\input{task-3} + +\subsubsection{Task 4: \textit{HAS back-end}} +%\input{task-4} + +\subsubsection{Task 5: \textit{Communication between PC \& FPGA-SoC}} +\input{task-5} + +\subsubsection{Task 6: \textit{Demonstrators}} +\input{task-6} \subsection{Tasks schedule, deliverables and milestones} Index: /anr/section-4.1.tex =================================================================== --- /anr/section-4.1.tex (revision 22) +++ /anr/section-4.1.tex (revision 23) @@ -94,5 +94,5 @@ partitioning validation (see figure~\ref{archi-hpc}, the sytem drivers for both PC and FPGA-SoC sides, the hardware communication components. -\item\textbf{Demonstrator:} +\item\textbf{Demonstrators:} This task groups the demostrators of the COACH project. \mustbecompleted{FIXME} Index: /anr/task-2.tex =================================================================== --- /anr/task-2.tex (revision 23) +++ /anr/task-2.tex (revision 23) @@ -0,0 +1,69 @@ +\begin{taskinfo} +\let\UPMC\leader +\let\IRISA\enable +\let\TIMA\ensable +\end{taskinfo} +% +\begin{objectif} +This task relies to the prototyping and the generation of FPGA-SoC digital systems. +Its is described on figure~\ref{arci-csg} and it consists of +Its objective is to allows the system designer to explore the system space design by quickly prototyping and then to generate automatically the FPGA-SoC system. +This task consists of +\begin{itemize} +\item the development of all the missing components (SytemC model and/or synthesizable VHDL description), +\item the configuration and the development of drivers of the operating systems, +\item the CSG software that generates the simulators for prototiping and the FPGA-SoC system, +\item the specification of enhanced communication schem and their sofware and hardware implementation. +\end{itemize} +This task being based on the SocLib platform, a first release will be delivrable at $T0+12$ +to allow the demonstrators to start working. +This release will include the standard communication schems (base on SocLib MWMR component) +and support the COACH architectural template for prototyping and hardware generation. +\end{objectif} +% +\begin{workpackage}{T2} +\item This \ST corresponds to the Coach System Generator (DSG) software. + \begin{livrable} + \item{-V1}{0}{12}{x}{\upmc}{DSG} The first milestone that will allow demonstrators to + start working using the COACH hardware architecture template. + \item{-V2}{0}{24}{x}{\upmc}{DSG} This milestone adds to DSG the support to the Xilinx + and Altera architectural templates and to the enhanced communication system. + \item{-VF}{0}{36}{x}{\upmc}{DSG} The final release. + \end{livrable} +\item This \ST relies to the components of the Coach architectural template. + \begin{livrable} + \item{-VF}{0}{12}{x}{\upmc}{COACH architecture} The VHDL synthesizable description + of the SocLib MWMR, TokenRing. + \end{livrable} +\item This \ST consists of the configuration of the SocLib Mutek operating system and the + development of drivers for the hardware architectural template and enhanced + communication schems. + \begin{livrable} + \item{-V1}{0}{12}{x}{\upmc}{Mutek OS} The first milestone required by \ST T2-1-V1. + \item{-V2}{0}{24}{x}{\upmc}{Mutek 0S} This milestone required by \ST T2-1-V2. + \item{-VF}{0}{36}{x}{\upmc}{Mutek OS} The final release. + \end{livrable} +\item This \ST consists of the configuration of the SocLib DNA operating system and the + development of drivers for the hardware architectural template and enhanced + communication schems. + \begin{livrable} + \item{-V1}{0}{12}{x}{\tima}{DNA OS} The first milestone required by \ST T2-1-V1. + \item{-V2}{0}{24}{x}{\tima}{DNA 0S} This milestone required by \ST T2-1-V2. + \item{-VF}{0}{36}{x}{\tima}{DNA OS} The final release. + \end{livrable} +\item This \ST relies to definition and implementation of the enhanced communication + schems usable in the definition of communicante task graph. + \begin{livrable} + \item{-VF}{0}{6}{d}{\tima}{CSG user manual} A document that describes the CSG task + graph inputs (task graph, task description, communication schems). + \end{livrable} +\item This \ST relies to implementation of the MWMR component for the Xilinx and Altera + architectural template. + \begin{livrable} + \item{-1-VF}{0}{18}{x}{\tima}{MWMR Altera} The VHDL synthesizable description and + SystemC model of the MWMR with a PLB bus interface. + \item{-2-VF}{0}{18}{x}{\irisa}{MWMR Altera} The VHDL synthesizable description and + SystemC model of the MWMR with an AVALON bus interface. + \end{livrable} +% FIXME:CITI +\end{workpackage} Index: /anr/task-5.tex =================================================================== --- /anr/task-5.tex (revision 23) +++ /anr/task-5.tex (revision 23) @@ -0,0 +1,60 @@ +\begin{taskinfo} +\let\UPMC\leader +\let\TIMA\enable +\let\ALTERA\enable +\end{taskinfo} +% +\begin{objectif} +This task pools the features dedicated to HPC system design. It is described on +figures~\ref{coach-flow} and \ref{archi-hpc}. It consists in +\begin{itemize} +\item Helping the HPC designer to find a good partition of the initial application + (figure~\ref{archi-hpc}. +\item Providing communication schems between the software part runing on the PC and the +FPGA-SoC. +\item Implementing the communication schem at all levels: partition help, software +implementation both on the PC and in the operating system of the FPGA-SoC, hardware. +\item FPGA reconfiguration. \mustbecompleted{FIXME:TIMA} +\end{itemize} +The low level hardware transmission support will be the PCI/X bus which allows high bit-rate +transfers. The reasons of this choices are that both ALTERA and Xilinx provide PCI/X IP for +their FPGA and that GPU HPC softwares use also it. +This will allow us at least to be inspired by GPU communication schems and may be to reuse +parts of the GPU softwares. +\end{objectif} +% +\begin{workpackage}{T5} +\item This \ST is the definition of the communication schems as a software API + (Application Programing Interface) between the application part running on the PC and + the application part running on the FPGA-SoC. + \begin{livrable} + \item{-VF}{0}{6}{d}{\upmc}{HPC communication API} User refernce manual describing the API. + \end{livrable} +\item This \ST aims with the application partitioning help. It is a library implementing + the communication API with features to profile the application partionning. + \begin{livrable} + \item{-VF}{0}{12}{x}{\upmc}{HPC partionning help} A library. + \end{livrable} +\item This \ST aims with the implementation of the communication API on the both sides (PC + part and FPGA-SoC). + \begin{livrable} + \item{-1-VF}{0}{21}{x}{\upmc}{HPC API for Linux PC} + \item{-2-VF}{0}{21}{x}{\tima}{HPC API for DNA OS} + \item{-3-VF}{0}{21}{x}{\upmc}{HPC API for Mutek OS} + \end{livrable} +\item This \ST aims with the implementation of hardware required by the COACH + architectural template for using the PCI/X IP of \altera and \xilinx. + \begin{livrable} + \item{-1-VF}{0}{21}{h}{\tima}{HPC hardwre \xilinx} A synthesizable VHDL description + of a PLB/VCI bridge. + \item{-1-VF}{0}{21}{h}{\altera}{HPC hardwre \altera} A synthesizable VHDL description + of a AVALON/VCI bridge. + \end{livrable} +\item This \ST aims with the dynamic reconfiguration of FPGA. + \begin{livrable} + \item{-1-VF}{0}{30}{x}{\tima}{dynamic reconfiguration DNA drivers} + \item{-2-VF}{0}{30}{x}{\upmc}{dynamic reconfiguration mutek drivers} + \item{-3-VF}{0}{30}{x}{\upmc}{CSG support for dynamic reconfiguration} + \item{-3-VF}{0}{30}{x}{\tima}{PC support for dynamic reconfiguration} + \end{livrable} +\end{workpackage} Index: /anr/task-6.tex =================================================================== --- /anr/task-6.tex (revision 23) +++ /anr/task-6.tex (revision 23) @@ -0,0 +1,29 @@ +\begin{taskinfo} +\let\IRISA\leader +\let\UPMC\enable +\end{taskinfo} +% +\begin{objectif} +This task groups the demonstrators of the COACH project. +The demonstrators cover various domains and application types to drive +the specification choices. +\end{objectif} +% +\begin{workpackage}{T6} +\item This \ST is the reference demonstrator. It is a HPC application and so it covers + in addition to HPC (task-5) both the system genration (task-2), the HAS (task-3) and (task-4). + The reference demonstrator can be a Motion JPEG application, + or an application that draws in 3D (under open GL) a metor cloud attracted by a sun an + planets, + or a database management system. + \begin{livrable} + \item{-V1}{0}{6}{x}{\upmc}{reference demonstrator} Choice of the demonstrator and its + implementation as a PC C/C++ program. + \item{-VF}{0}{12}{x}{\upmc}{partitionned reference demonstrator} The demonstrator + splited into 2 parts, a description as communicante task graph of the FPGA-SoC part. + \end{livrable} +\end{workpackage} + + + +